From d538367ebd20fbf9c2adb96efd0457487c6b0b28 Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Wed, 26 Oct 2022 15:50:44 +0530 Subject: [PATCH] disp: rsc: update mode-1 threshold config to 1 hz Update mode-1 threshold configuration to 1 hz to avoid selecting mode-2 if panel vsync is irregular. Change-Id: I9d48d088ac1e84f9d0e422d006458527e1944ed8 Signed-off-by: Dhaval Patel Signed-off-by: Mahadevan --- msm/sde_rsc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/msm/sde_rsc.c b/msm/sde_rsc.c index 82aff0540f4d..6e5e3d33adf1 100644 --- a/msm/sde_rsc.c +++ b/msm/sde_rsc.c @@ -368,9 +368,8 @@ static u32 sde_rsc_timer_calculate(struct sde_rsc_priv *rsc, rsc_time_slot_0_ns = div_u64(rsc_time_slot_0_ns, cxo_period_ns); rsc->timer_config.rsc_time_slot_0_ns = (u32) rsc_time_slot_0_ns; - /* time_slot_1 for mode1 latency */ - rsc_time_slot_1_ns = frame_time_ns; - rsc_time_slot_1_ns = div_u64(rsc_time_slot_1_ns, cxo_period_ns); + /* time_slot_1 for mode1 latency - 1 fps */ + rsc_time_slot_1_ns = div_u64(TICKS_IN_NANO_SECOND, cxo_period_ns); rsc->timer_config.rsc_time_slot_1_ns = (u32) rsc_time_slot_1_ns; /* mode 2 is infinite */