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clk: qcom: lahaina: Lucid PLL 5LPE config and frequency plan update

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Lucid PLL 5LPE reduced Nominal FMax from 2000 to 1750MHz and SVS_L1 FMax
from 1600 to 1500Mhz.

Change-Id: I1d6a162aa6a268efb146ea19499e29caa6cbcfaa
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
This commit is contained in:
Vivek Aknurwar 2020-06-08 16:44:48 -07:00 • committed by Gerrit - the friendly Code Review server
commit d557d4dfe5
5 changed files with 73 additions and 47 deletions
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62
drivers/clk/qcom/camcc-lahaina.c
View file

@ -49,7 +49,7 @@ enum {
};
static struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 2000000000, 0 },
{ 249600000, 1750000000, 0 },
};
static struct pll_vco zonda_5lpe_vco[] = {
@ -92,8 +92,8 @@ static struct clk_alpha_pll cam_cc_pll0 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -180,8 +180,8 @@ static struct clk_alpha_pll cam_cc_pll1 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -218,6 +218,15 @@ static const struct alpha_pll_config cam_cc_pll2_config = {
.config_ctl_hi1_val = 0x00000000,
};
static const struct alpha_pll_config cam_cc_pll2_config_sm8350_v2 = {
.l = 0x32,
.cal_l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x08200800,
.config_ctl_hi_val = 0x05028011,
.config_ctl_hi1_val = 0x08000000,
};
static struct clk_alpha_pll cam_cc_pll2 = {
.offset = 0x2000,
.vco_table = zonda_5lpe_vco,
@ -281,8 +290,8 @@ static struct clk_alpha_pll cam_cc_pll3 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -346,8 +355,8 @@ static struct clk_alpha_pll cam_cc_pll4 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -411,8 +420,8 @@ static struct clk_alpha_pll cam_cc_pll5 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -476,8 +485,8 @@ static struct clk_alpha_pll cam_cc_pll6 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -2975,10 +2984,33 @@ static const struct qcom_cc_desc cam_cc_lahaina_desc = {
static const struct of_device_id cam_cc_lahaina_match_table[] = {
{ .compatible = "qcom,lahaina-camcc" },
{ .compatible = "qcom,lahaina-camcc-v2" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_cc_lahaina_match_table);
static void cam_cc_lahaina_fixup_lahainav2(struct regmap *regmap)
{
clk_zonda_5lpe_pll_configure(&cam_cc_pll2, regmap,
&cam_cc_pll2_config_sm8350_v2);
}
static int cam_cc_lahaina_fixup(struct platform_device *pdev,
struct regmap *regmap)
{
const char *compat = NULL;
int compatlen = 0;
compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);
if (!compat || (compatlen <= 0))
return -EINVAL;
if (!strcmp(compat, "qcom,lahaina-camcc-v2"))
cam_cc_lahaina_fixup_lahainav2(regmap);
return 0;
}
static int cam_cc_lahaina_probe(struct platform_device *pdev)
{
struct regmap *regmap;
@ -3007,6 +3039,10 @@ static int cam_cc_lahaina_probe(struct platform_device *pdev)
clk_lucid_5lpe_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
clk_lucid_5lpe_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
ret = cam_cc_lahaina_fixup(pdev, regmap);
if (ret)
return ret;
ret = qcom_cc_really_probe(pdev, &cam_cc_lahaina_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register CAM CC clocks\n");

10
drivers/clk/qcom/dispcc-lahaina.c
View file

@ -54,7 +54,7 @@ enum {
};
static struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 2000000000, 0 },
{ 249600000, 1750000000, 0 },
};
static const struct alpha_pll_config disp_cc_pll0_config = {
@ -93,8 +93,8 @@ static struct clk_alpha_pll disp_cc_pll0 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -135,8 +135,8 @@ static struct clk_alpha_pll disp_cc_pll1 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};

22
drivers/clk/qcom/gcc-lahaina.c
View file

@ -54,14 +54,8 @@ enum {
P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
};
static struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct clk_alpha_pll gcc_gpll0 = {
.offset = 0x0,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_5LPE],
.clkr = {
.enable_reg = 0x52018,
@ -81,8 +75,8 @@ static struct clk_alpha_pll gcc_gpll0 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -111,8 +105,6 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
static struct clk_alpha_pll gcc_gpll4 = {
.offset = 0x76000,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_5LPE],
.clkr = {
.enable_reg = 0x52018,
@ -132,16 +124,14 @@ static struct clk_alpha_pll gcc_gpll4 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
static struct clk_alpha_pll gcc_gpll9 = {
.offset = 0x1c000,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_5LPE],
.clkr = {
.enable_reg = 0x52018,
@ -161,8 +151,8 @@ static struct clk_alpha_pll gcc_gpll9 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};

16
drivers/clk/qcom/gpucc-lahaina.c
View file

@ -28,8 +28,8 @@ static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NOMINAL + 1, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NOMINAL + 1, 1, vdd_corner);
static struct clk_vdd_class *gpu_cc_lahaina_regulators[] = {
&vdd_mx,
&vdd_cx,
&vdd_mx,
};
enum {
@ -42,7 +42,7 @@ enum {
};
static struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 2000000000, 0 },
{ 249600000, 1750000000, 0 },
};
static const struct alpha_pll_config gpu_cc_pll0_config = {
@ -81,8 +81,8 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -123,8 +123,8 @@ static struct clk_alpha_pll gpu_cc_pll1 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -191,7 +191,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 200000000,
[VDD_LOWER] = 200000000,
[VDD_LOW] = 500000000},
},
};
@ -222,7 +222,7 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 150000000,
[VDD_LOWER] = 150000000,
[VDD_LOW] = 240000000,
[VDD_NOMINAL] = 300000000},
},

10
drivers/clk/qcom/videocc-lahaina.c
View file

@ -41,7 +41,7 @@ enum {
};
static struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 2000000000, 0 },
{ 249600000, 1750000000, 0 },
};
static const struct alpha_pll_config video_pll0_config = {
@ -80,8 +80,8 @@ static struct clk_alpha_pll video_pll0 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};
@ -122,8 +122,8 @@ static struct clk_alpha_pll video_pll1 = {
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000},
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1750000000},
},
},
};