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usb: dwc3: add global soc bus configuration reg0

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Add the macro definition for global soc bus configuration
register 0

Signed-off-by: Changming Huang <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
Signed-off-by: Pengbo Mu <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
This commit is contained in:
Pengbo Mu 2018-07-23 18:32:36 +08:00 • committed by Felipe Balbi
commit d635db5508
1 changed files with 11 additions and 0 deletions
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11
drivers/usb/dwc3/core.h
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@ -163,6 +163,17 @@
/* Bit fields */
/* Global SoC Bus Configuration INCRx Register 0 */
#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
/* Global Debug Queue/FIFO Space Available Register */
#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)