From 3fbc552f68992d37f51cb1a44b7fd37da123dccf Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Mon, 25 Jan 2021 09:37:38 +0800 Subject: [PATCH] ARM: dts: msm: Add device trees for sa8195 virtual machine Add device tree files for sa8195 virtual machine. Change-Id: I252468bee7256b5a66944cadd4a345695a0c84c5 --- qcom/Makefile | 7 +- qcom/sa8195-vm-la-mt.dts | 11 + qcom/sa8195-vm-la-mt.dtsi | 6 + qcom/sa8195-vm-la.dts | 11 + qcom/sa8195-vm-la.dtsi | 30 + qcom/sa8195-vm-lv-lxc.dts | 11 + qcom/sa8195-vm-lv-lxc.dtsi | 39 ++ qcom/sa8195-vm-lv-mt.dts | 11 + qcom/sa8195-vm-lv-mt.dtsi | 34 + qcom/sa8195-vm-lv.dts | 11 + qcom/sa8195-vm-lv.dtsi | 30 + qcom/sa8195-vm-pcie.dtsi | 1303 ++++++++++++++++++++++++++++++++++++ qcom/sa8195-vm-usb.dtsi | 201 ++++++ qcom/sa8195-vm.dtsi | 468 +++++++++++++ 14 files changed, 2172 insertions(+), 1 deletion(-) create mode 100644 qcom/sa8195-vm-la-mt.dts create mode 100644 qcom/sa8195-vm-la-mt.dtsi create mode 100644 qcom/sa8195-vm-la.dts create mode 100644 qcom/sa8195-vm-la.dtsi create mode 100644 qcom/sa8195-vm-lv-lxc.dts create mode 100644 qcom/sa8195-vm-lv-lxc.dtsi create mode 100644 qcom/sa8195-vm-lv-mt.dts create mode 100644 qcom/sa8195-vm-lv-mt.dtsi create mode 100644 qcom/sa8195-vm-lv.dts create mode 100644 qcom/sa8195-vm-lv.dtsi create mode 100644 qcom/sa8195-vm-pcie.dtsi create mode 100644 qcom/sa8195-vm-usb.dtsi create mode 100644 qcom/sa8195-vm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 161b3dc1b925..ddee39dfa495 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -314,7 +314,12 @@ endif dtb-$(CONFIG_QTI_QUIN_GVM) += sa8155-vm-la.dtb \ sa8155-vm-lv.dtb \ sa8155-vm-la-mt.dtb \ - sa8155-vm-lv-mt.dtb + sa8155-vm-lv-mt.dtb \ + sa8195-vm-la.dtb \ + sa8195-vm-lv.dtb \ + sa8195-vm-la-mt.dtb \ + sa8195-vm-lv-mt.dtb \ + sa8195-vm-lv-lxc.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/qcom/sa8195-vm-la-mt.dts b/qcom/sa8195-vm-la-mt.dts new file mode 100644 index 000000000000..caea45b3efe5 --- /dev/null +++ b/qcom/sa8195-vm-la-mt.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195-vm.dtsi" +#include "sa8195-vm-la-mt.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Multi LA Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0x2000001 0>; +}; diff --git a/qcom/sa8195-vm-la-mt.dtsi b/qcom/sa8195-vm-la-mt.dtsi new file mode 100644 index 000000000000..e975abfa0bd4 --- /dev/null +++ b/qcom/sa8195-vm-la-mt.dtsi @@ -0,0 +1,6 @@ +&reserved_memory { + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; diff --git a/qcom/sa8195-vm-la.dts b/qcom/sa8195-vm-la.dts new file mode 100644 index 000000000000..5413244629e4 --- /dev/null +++ b/qcom/sa8195-vm-la.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195-vm.dtsi" +#include "sa8195-vm-la.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Single LA Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0x1000001 0>; +}; diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi new file mode 100644 index 000000000000..7d003a2eb6b1 --- /dev/null +++ b/qcom/sa8195-vm-la.dtsi @@ -0,0 +1,30 @@ +&reserved_memory { + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&sdhc_2 { + status = "ok"; +}; diff --git a/qcom/sa8195-vm-lv-lxc.dts b/qcom/sa8195-vm-lv-lxc.dts new file mode 100644 index 000000000000..d4b58dc6e970 --- /dev/null +++ b/qcom/sa8195-vm-lv-lxc.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195-vm.dtsi" +#include "sa8195-vm-lv-lxc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Multi LV Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0x2000002 0>; +}; diff --git a/qcom/sa8195-vm-lv-lxc.dtsi b/qcom/sa8195-vm-lv-lxc.dtsi new file mode 100644 index 000000000000..75228e2e38af --- /dev/null +++ b/qcom/sa8195-vm-lv-lxc.dtsi @@ -0,0 +1,39 @@ +/ { + /delete-node/ cpus; +}; + +&hab { + vmid = <3>; +}; + +&reserved_memory { + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; + +&usb0 { + status = "ok"; +}; + +&usb1 { + qcom,default-mode-host; + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&pcie2_msi { + status = "ok"; +}; + +&pcie2 { + status = "ok"; +}; diff --git a/qcom/sa8195-vm-lv-mt.dts b/qcom/sa8195-vm-lv-mt.dts new file mode 100644 index 000000000000..ee43c89ff38f --- /dev/null +++ b/qcom/sa8195-vm-lv-mt.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195-vm.dtsi" +#include "sa8195-vm-lv-mt.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Multi LV Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0x2000002 0>; +}; diff --git a/qcom/sa8195-vm-lv-mt.dtsi b/qcom/sa8195-vm-lv-mt.dtsi new file mode 100644 index 000000000000..35a59df5dedf --- /dev/null +++ b/qcom/sa8195-vm-lv-mt.dtsi @@ -0,0 +1,34 @@ +/ { + /delete-node/ cpus; +}; + +&hab { + vmid = <3>; +}; + +&reserved_memory { + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; diff --git a/qcom/sa8195-vm-lv.dts b/qcom/sa8195-vm-lv.dts new file mode 100644 index 000000000000..9dd5fe872ef0 --- /dev/null +++ b/qcom/sa8195-vm-lv.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195-vm.dtsi" +#include "sa8195-vm-lv.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Single LV Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0x1000002 0>; +}; diff --git a/qcom/sa8195-vm-lv.dtsi b/qcom/sa8195-vm-lv.dtsi new file mode 100644 index 000000000000..f7fd0e816130 --- /dev/null +++ b/qcom/sa8195-vm-lv.dtsi @@ -0,0 +1,30 @@ +&hab { + vmid = <3>; +}; + +&reserved_memory { + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; +}; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; diff --git a/qcom/sa8195-vm-pcie.dtsi b/qcom/sa8195-vm-pcie.dtsi new file mode 100644 index 000000000000..44c9d2b10f62 --- /dev/null +++ b/qcom/sa8195-vm-pcie.dtsi @@ -0,0 +1,1303 @@ +#include +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c06000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0xc0 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x0d 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x88 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x840>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2110>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d80>; + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>, + <0x200 &apps_smmu 0x1d82 0x1>, + <0x300 &apps_smmu 0x1d83 0x1>, + <0x400 &apps_smmu 0x1d84 0x1>, + <0x500 &apps_smmu 0x1d85 0x1>, + <0x600 &apps_smmu 0x1d86 0x1>, + <0x700 &apps_smmu 0x1d87 0x1>, + <0x800 &apps_smmu 0x1d88 0x1>, + <0x900 &apps_smmu 0x1d89 0x1>, + <0xa00 &apps_smmu 0x1d8a 0x1>, + <0xb00 &apps_smmu 0x1d8b 0x1>, + <0xc00 &apps_smmu 0x1d8c 0x1>, + <0xd00 &apps_smmu 0x1d8d 0x1>, + <0xe00 &apps_smmu 0x1d8e 0x1>, + <0xf00 &apps_smmu 0x1d8f 0x1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + status = "disabled"; + + pcie_rc0: pcie_rc0 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + + pcie1: qcom,pcie@1c10000 { + compatible = "qcom,pci-msm"; + cell-index = <1>; + + reg = <0x1c10000 0x3000>, + <0x01c16000 0x2000>, + <0x68000000 0xf1d>, + <0x68000f20 0xa8>, + <0x68001000 0x1000>, + <0x68100000 0x100000>, + <0x68200000 0x100000>, + <0x68300000 0x3d00000>, + <0x01fec004 0x4>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars", "tcsr"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x68200000 0x68200000 0x0 0x100000>, + <0x02000000 0x0 0x68300000 0x68300000 0x0 0x3d00000>; + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; + + qcom,tcsr = <0x0 0x0>; + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x35 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x063c 0x11 0x0 + 0x0684 0x35 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x01 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0eb4 0x33 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_default + &pcie1_perst_default + &pcie1_wake_default>; + + perst-gpio = <&tlmm 175 0>; + wake-gpio = <&tlmm 177 0>; + + gdsc-vdd-supply = <&pcie_1_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie1_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <1>; + + qcom,pcie-phy-ver = <2113>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1c80>; + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x200 &apps_smmu 0x1c82 0x1>, + <0x300 &apps_smmu 0x1c83 0x1>, + <0x400 &apps_smmu 0x1c84 0x1>, + <0x500 &apps_smmu 0x1c85 0x1>, + <0x600 &apps_smmu 0x1c86 0x1>, + <0x700 &apps_smmu 0x1c87 0x1>, + <0x800 &apps_smmu 0x1c88 0x1>, + <0x900 &apps_smmu 0x1c89 0x1>, + <0xa00 &apps_smmu 0x1c8a 0x1>, + <0xb00 &apps_smmu 0x1c8b 0x1>, + <0xc00 &apps_smmu 0x1c8c 0x1>, + <0xd00 &apps_smmu 0x1c8d 0x1>, + <0xe00 &apps_smmu 0x1c8e 0x1>, + <0xf00 &apps_smmu 0x1c8f 0x1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", + "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk", + "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk", + "pcie_1_ldo", "pcie_1_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>; + + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset"; + + status = "disabled"; + + pcie_rc1: pcie_rc1 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie1_msi: qcom,pcie1_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + + pcie2: qcom,pcie@1c18000 { + compatible = "qcom,pci-msm"; + cell-index = <2>; + + reg = <0x1c18000 0x3000>, + <0x01c1c000 0x2000>, + <0x70000000 0xf1d>, + <0x70000f20 0xa8>, + <0x70001000 0x1000>, + <0x70100000 0x100000>, + <0x70200000 0x100000>, + <0x70300000 0x3d00000>, + <0x01fec004 0x4>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars", "tcsr"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x70200000 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x70300000 0x0 0x3d00000>; + interrupt-parent = <&pcie2>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; + + qcom,tcsr = <0x0 0x0>; + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x35 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x063c 0x11 0x0 + 0x0684 0x35 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x01 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0eb4 0x33 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_clkreq_default + &pcie2_perst_default + &pcie2_wake_default>; + + perst-gpio = <&tlmm 102 0>; + wake-gpio = <&tlmm 104 0>; + + gdsc-vdd-supply = <&pcie_2_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie2_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <2>; + + qcom,pcie-phy-ver = <2105>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d00>; + + iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, + <0x100 &apps_smmu 0x1d01 0x1>, + <0x200 &apps_smmu 0x1d02 0x1>, + <0x300 &apps_smmu 0x1d03 0x1>, + <0x400 &apps_smmu 0x1d04 0x1>, + <0x500 &apps_smmu 0x1d05 0x1>, + <0x600 &apps_smmu 0x1d06 0x1>, + <0x700 &apps_smmu 0x1d07 0x1>, + <0x800 &apps_smmu 0x1d08 0x1>, + <0x900 &apps_smmu 0x1d09 0x1>, + <0xa00 &apps_smmu 0x1d0a 0x1>, + <0xb00 &apps_smmu 0x1d0b 0x1>, + <0xc00 &apps_smmu 0x1d0c 0x1>, + <0xd00 &apps_smmu 0x1d0d 0x1>, + <0xe00 &apps_smmu 0x1d0e 0x1>, + <0xf00 &apps_smmu 0x1d0f 0x1>; + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src", + "pcie_2_aux_clk", "pcie_2_cfg_ahb_clk", + "pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk", + "pcie_2_ldo", "pcie_2_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_2_BCR>, + <&gcc GCC_PCIE_2_PHY_BCR>; + + reset-names = "pcie_2_core_reset", + "pcie_2_phy_reset"; + + status = "disabled"; + + pcie_rc2: pcie_rc2 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie2_msi: qcom,pcie2_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + + pcie3: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <3>; + + reg = <0x1c08000 0x3000>, + <0x1c0c000 0x4000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupt-parent = <&pcie3>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0044 0x1c 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x029c 0x12 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x0684 0x35 0x0 + 0x063c 0x11 0x0 + 0x069c 0x12 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x01 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0eb4 0x33 0x0 + 0x2a40 0x03 0x0 + 0x2010 0x00 0x0 + 0x201c 0x31 0x0 + 0x2020 0x01 0x0 + 0x2024 0xde 0x0 + 0x2028 0x07 0x0 + 0x2030 0x4c 0x0 + 0x2034 0x06 0x0 + 0x2048 0x90 0x0 + 0x2044 0x1c 0x0 + 0x2058 0x0f 0x0 + 0x2074 0x06 0x0 + 0x2078 0x06 0x0 + 0x207c 0x16 0x0 + 0x2080 0x16 0x0 + 0x2084 0x36 0x0 + 0x2088 0x36 0x0 + 0x2094 0x08 0x0 + 0x20a4 0x42 0x0 + 0x20ac 0x0a 0x0 + 0x20b0 0x1a 0x0 + 0x20b4 0x14 0x0 + 0x20b8 0x34 0x0 + 0x20bc 0x82 0x0 + 0x20c4 0x68 0x0 + 0x20cc 0x55 0x0 + 0x20d0 0x55 0x0 + 0x20d4 0x03 0x0 + 0x20d8 0xab 0x0 + 0x20dc 0xaa 0x0 + 0x20e0 0x02 0x0 + 0x210c 0x02 0x0 + 0x2110 0x24 0x0 + 0x2118 0xb4 0x0 + 0x211c 0x03 0x0 + 0x2154 0x34 0x0 + 0x2158 0x01 0x0 + 0x216c 0x08 0x0 + 0x21ac 0xb9 0x0 + 0x21b0 0x1e 0x0 + 0x21b4 0x94 0x0 + 0x21b8 0x18 0x0 + 0x21bc 0x11 0x0 + 0x2284 0x35 0x0 + 0x223c 0x11 0x0 + 0x229c 0x12 0x0 + 0x2408 0x0c 0x0 + 0x2414 0x03 0x0 + 0x2434 0x7f 0x0 + 0x2444 0x70 0x0 + 0x2460 0x30 0x0 + 0x2464 0x00 0x0 + 0x24d4 0x54 0x0 + 0x24d8 0x07 0x0 + 0x24dc 0x0d 0x0 + 0x24e8 0x00 0x0 + 0x24ec 0x0e 0x0 + 0x24f0 0x4a 0x0 + 0x24f4 0x0f 0x0 + 0x24f8 0xc0 0x0 + 0x24fc 0x00 0x0 + 0x2510 0x17 0x0 + 0x2518 0x1c 0x0 + 0x251c 0x03 0x0 + 0x2524 0x1e 0x0 + 0x2570 0xff 0x0 + 0x2574 0xff 0x0 + 0x2578 0xff 0x0 + 0x257c 0x7f 0x0 + 0x2580 0x66 0x0 + 0x2584 0x24 0x0 + 0x2588 0xe4 0x0 + 0x258c 0xec 0x0 + 0x2590 0x3b 0x0 + 0x2594 0x36 0x0 + 0x2598 0xd4 0x0 + 0x259c 0x54 0x0 + 0x25a0 0xdb 0x0 + 0x25a4 0x3b 0x0 + 0x25a8 0x31 0x0 + 0x25bc 0x0c 0x0 + 0x2684 0x35 0x0 + 0x263c 0x11 0x0 + 0x269c 0x12 0x0 + 0x2808 0x0c 0x0 + 0x2814 0x03 0x0 + 0x2834 0x7f 0x0 + 0x2844 0x70 0x0 + 0x2860 0x30 0x0 + 0x2864 0x00 0x0 + 0x28d4 0x54 0x0 + 0x28d8 0x07 0x0 + 0x28dc 0x0d 0x0 + 0x28e8 0x00 0x0 + 0x28ec 0x0e 0x0 + 0x28f0 0x4a 0x0 + 0x28f4 0x0f 0x0 + 0x28f8 0xc0 0x0 + 0x28fc 0x00 0x0 + 0x2910 0x17 0x0 + 0x2918 0x1c 0x0 + 0x291c 0x03 0x0 + 0x2924 0x1e 0x0 + 0x2970 0xff 0x0 + 0x2974 0xff 0x0 + 0x2978 0xff 0x0 + 0x297c 0x7f 0x0 + 0x2980 0x66 0x0 + 0x2984 0x24 0x0 + 0x2988 0xe4 0x0 + 0x298c 0xec 0x0 + 0x2990 0x3b 0x0 + 0x2994 0x36 0x0 + 0x2998 0xd4 0x0 + 0x299c 0x54 0x0 + 0x29a0 0xdb 0x0 + 0x29a4 0x3b 0x0 + 0x29a8 0x31 0x0 + 0x29bc 0x0c 0x0 + 0x2adc 0x05 0x0 + 0x2b88 0x88 0x0 + 0x2b98 0x0b 0x0 + 0x2ba4 0x01 0x0 + 0x2bec 0x01 0x0 + 0x2e0c 0x0d 0x0 + 0x2e14 0x07 0x0 + 0x2e1c 0xc1 0x0 + 0x2e40 0x01 0x0 + 0x2e48 0x01 0x0 + 0x2e90 0x00 0x0 + 0x2ebc 0x00 0x0 + 0x2ee0 0x58 0x0 + 0x2eb4 0x33 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_clkreq_default + &pcie3_perst_default + &pcie3_wake_default>; + + perst-gpio = <&tlmm 178 0>; + wake-gpio = <&tlmm 56 0>; + + gdsc-vdd-supply = <&pcie_3_gdsc>; + vreg-1p8-supply = <&pm8195_1_l9>; + vreg-0p9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie3_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <3>; + + qcom,pcie-phy-ver = <2105>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1e00>; + + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>, + <0x200 &apps_smmu 0x1e02 0x1>, + <0x300 &apps_smmu 0x1e03 0x1>, + <0x400 &apps_smmu 0x1e04 0x1>, + <0x500 &apps_smmu 0x1e05 0x1>, + <0x600 &apps_smmu 0x1e06 0x1>, + <0x700 &apps_smmu 0x1e07 0x1>, + <0x800 &apps_smmu 0x1e08 0x1>, + <0x900 &apps_smmu 0x1e09 0x1>, + <0xa00 &apps_smmu 0x1e0a 0x1>, + <0xb00 &apps_smmu 0x1e0b 0x1>, + <0xc00 &apps_smmu 0x1e0c 0x1>, + <0xd00 &apps_smmu 0x1e0d 0x1>, + <0xe00 &apps_smmu 0x1e0e 0x1>, + <0xf00 &apps_smmu 0x1e0f 0x1>; + + clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_3_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_3_pipe_clk", "pcie_3_ref_clk_src", + "pcie_3_aux_clk", "pcie_3_cfg_ahb_clk", + "pcie_3_mstr_axi_clk", "pcie_3_slv_axi_clk", + "pcie_3_ldo", "pcie_3_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_3_BCR>, + <&gcc GCC_PCIE_3_PHY_BCR>; + + reset-names = "pcie_3_core_reset", + "pcie_3_phy_reset"; + + status = "disabled"; + + pcie_rc3: pcie_rc3 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0109"; + }; + }; + + pcie3_msi: qcom,pcie3_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; +}; diff --git a/qcom/sa8195-vm-usb.dtsi b/qcom/sa8195-vm-usb.dtsi new file mode 100644 index 000000000000..7d27d7c212d3 --- /dev/null +++ b/qcom/sa8195-vm-usb.dtsi @@ -0,0 +1,201 @@ +#include +#include +#include +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&dummycc RPMH_CXO_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + + qcom,charging-disabled; + qcom,ignore-wakeup-src-in-hostmode; + + status = "disabled"; + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e2000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e2000 0x110>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x160 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&dummycc RPMH_CXO_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,charging-disabled; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <1>; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x110>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + + status = "disabled"; + }; +}; diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi new file mode 100644 index 000000000000..19700893437d --- /dev/null +++ b/qcom/sa8195-vm.dtsi @@ -0,0 +1,468 @@ +#include +#include +#include +#include +#include +#include +#include +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Virtual Machine"; + qcom,msm-name = "SA8195P"; + qcom,msm-id = <405 0x20000>; + aliases { + hsuart0 = &qupv3_se13_4uart; + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <1024>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <1024>; + }; + + CPU4: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x4>; + capacity-dmips-mhz = <306>; + }; + + CPU5: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x5>; + capacity-dmips-mhz = <306>; + }; + + CPU6: cpu@6 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x6>; + capacity-dmips-mhz = <306>; + }; + + CPU7: cpu@7 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x7>; + capacity-dmips-mhz = <306>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; +}; + +&soc { + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + qcom,restore-after-cx-collapse; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 25 MB/s */ + <65360 100000>, <100000 100000>, + /* 50 MB/s */ + <130718 200000>, <100000 100000>, + /* 100 MB/s */ + <261438 200000>, <130000 130000>, + /* 200 MB/s */ + <261438 400000>, <300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 200000000>; + + vdd-supply = <&pm8195_1_l10>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8195_1_l2>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + broken-cd; + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <70>; + }; + + qos1 { + mask = <0xf0>; + vote = <70>; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8150-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <6 486 6>, <30 510 1>, <40 520 1>, <46 526 1>, + <59 539 1>, <68 548 1>, <71 551 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + VDD_CX_LEVEL: + S3E_LEVEL: pm8195_3_s3_level: regulator-pm8195-3-s3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8195_3_s3_level"; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; +}; + +®ulator { + usb30_prim_gdsc: usb30_prim_gdsc { + regulator-name = "usb30_prim_gdsc"; + }; + + usb30_sec_gdsc: usb30_sec_gdsc { + regulator-name = "usb30_sec_gdsc"; + }; + + pcie_0_gdsc: pcie_0_gdsc { + regulator-name = "pcie_0_gdsc"; + }; + + pcie_1_gdsc: pcie_1_gdsc { + regulator-name = "pcie_1_gdsc"; + }; + + pcie_2_gdsc: pcie_2_gdsc { + regulator-name = "pcie_2_gdsc"; + }; + + pcie_3_gdsc: pcie_3_gdsc { + regulator-name = "pcie_3_gdsc"; + }; + + L2A: pm8195_1_l2: regulator-pm8195-1-l2 { + regulator-name = "ldoa2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + L9A: pm8195_1_l9: regulator-pm8195-1-l9 { + regulator-name = "ldoa9"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-allow-set-load; + }; + + L10A: pm8195_1_l10: regulator-pm8195-1-l10 { + regulator-name = "ldoa10"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L12A: pm8195_1_l12: regulator-pm8195-1-l12 { + regulator-name = "ldoa12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + }; + + L7C: pm8195_2_l7: regulator-pm8195-2-l7 { + regulator-name = "ldoc7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2040000>; + }; + + L5E: pm8195_3_l5: regulator-pm8195-3-l5 { + regulator-name = "ldoe5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + regulator-allow-set-load; + }; + + L16E: pm8195_3_l16: regulator-pm8195-3-l16 { + regulator-name = "ldoe16"; + regulator-min-microvolt = <2921000>; + regulator-max-microvolt = <3300000>; + }; + + S2A: pm8195_1_s2: regulator-pm8195-1-s2 { + regulator-name = "smpa2"; + regulator-min-microvolt = <1179000>; + regulator-max-microvolt = <1379000>; + }; + + S5A: pm8195_1_s5: regulator-pm8195-1-s5 { + regulator-name = "smpa5"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + }; + + S5C: pm8195_2_s5: regulator-pm8195-2-s5 { + regulator-name = "smpc5"; + regulator-min-microvolt = <1713000>; + regulator-max-microvolt = <2040000>; + }; +}; + +#include "sdmshrike-pinctrl.dtsi" +#include "sm8150-slpi-pinctrl.dtsi" +#include "sa8195-vm-usb.dtsi" +#include "sa8195-vm-pcie.dtsi" +#include "sa8195-qupv3.dtsi" +#include "sa8195-ssc-qupv3.dtsi" + +&tlmm { + /delete-property/ wakeup-parent; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&qupv3_0 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_1 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_2 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_3 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +};