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drm/i915/bdw: Add missing delay during L3 SQC credit programming

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BSpec requires us to wait ~100 clocks before re-enabling clock gating,
so make sure we do this.

CC: [email protected]
CC: Ville Syrjälä <[email protected]>
Signed-off-by: Imre Deak <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit 48e5d68d28)
Signed-off-by: Jani Nikula <[email protected]>
This commit is contained in:
Imre Deak 2016-05-03 15:54:19 +03:00 • committed by Jani Nikula
commit d6a862fe8c
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/i915/intel_pm.c
View file

@ -6646,6 +6646,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
misccpctl = I915_READ(GEN7_MISCCPCTL);
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
/*
* Wait at least 100 clocks before re-enabling clock gating. See
* the definition of L3SQCREG1 in BSpec.
*/
POSTING_READ(GEN8_L3SQCREG1);
udelay(1);
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
/*