mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
Merge with mainline to remove plat-omap/Kconfig conflict
Conflicts: arch/arm/plat-omap/Kconfig
This commit is contained in:
Tony Lindgren
commit
d702d12167
2770 changed files with 145422 additions and 54129 deletions
|
|
@ -251,12 +251,6 @@ config MTD_NETtel
|
|||
help
|
||||
Support for flash chips on NETtel/SecureEdge/SnapGear boards.
|
||||
|
||||
config MTD_ALCHEMY
|
||||
tristate "AMD Alchemy Pb1xxx/Db1xxx/RDK MTD support"
|
||||
depends on SOC_AU1X00 && MTD_PARTITIONS && MTD_CFI
|
||||
help
|
||||
Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards
|
||||
|
||||
config MTD_DILNETPC
|
||||
tristate "CFI Flash device mapped on DIL/Net PC"
|
||||
depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN
|
||||
|
|
|
|||
|
|
@ -40,7 +40,6 @@ obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx200_docflash.o
|
|||
obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o
|
||||
obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
|
||||
obj-$(CONFIG_MTD_PCI) += pci.o
|
||||
obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o
|
||||
obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
|
||||
obj-$(CONFIG_MTD_EDB7312) += edb7312.o
|
||||
obj-$(CONFIG_MTD_IMPA7) += impa7.o
|
||||
|
|
|
|||
|
|
@ -1,166 +0,0 @@
|
|||
/*
|
||||
* Flash memory access on AMD Alchemy evaluation boards
|
||||
*
|
||||
* (C) 2003, 2004 Pete Popov <ppopov@embeddedalley.com>
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/map.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_MIPS_PB1000
|
||||
#define BOARD_MAP_NAME "Pb1000 Flash"
|
||||
#define BOARD_FLASH_SIZE 0x00800000 /* 8MB */
|
||||
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_PB1500
|
||||
#define BOARD_MAP_NAME "Pb1500 Flash"
|
||||
#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
|
||||
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_PB1100
|
||||
#define BOARD_MAP_NAME "Pb1100 Flash"
|
||||
#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
|
||||
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_PB1550
|
||||
#define BOARD_MAP_NAME "Pb1550 Flash"
|
||||
#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
|
||||
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_PB1200
|
||||
#define BOARD_MAP_NAME "Pb1200 Flash"
|
||||
#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
|
||||
#define BOARD_FLASH_WIDTH 2 /* 16-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_DB1000
|
||||
#define BOARD_MAP_NAME "Db1000 Flash"
|
||||
#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
|
||||
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_DB1500
|
||||
#define BOARD_MAP_NAME "Db1500 Flash"
|
||||
#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
|
||||
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_DB1100
|
||||
#define BOARD_MAP_NAME "Db1100 Flash"
|
||||
#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
|
||||
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_DB1550
|
||||
#define BOARD_MAP_NAME "Db1550 Flash"
|
||||
#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
|
||||
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_DB1200
|
||||
#define BOARD_MAP_NAME "Db1200 Flash"
|
||||
#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
|
||||
#define BOARD_FLASH_WIDTH 2 /* 16-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_BOSPORUS
|
||||
#define BOARD_MAP_NAME "Bosporus Flash"
|
||||
#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */
|
||||
#define BOARD_FLASH_WIDTH 2 /* 16-bits */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_MIRAGE
|
||||
#define BOARD_MAP_NAME "Mirage Flash"
|
||||
#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
|
||||
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
|
||||
#define USE_LOCAL_ACCESSORS /* why? */
|
||||
#endif
|
||||
|
||||
static struct map_info alchemy_map = {
|
||||
.name = BOARD_MAP_NAME,
|
||||
};
|
||||
|
||||
static struct mtd_partition alchemy_partitions[] = {
|
||||
{
|
||||
.name = "User FS",
|
||||
.size = BOARD_FLASH_SIZE - 0x00400000,
|
||||
.offset = 0x0000000
|
||||
},{
|
||||
.name = "YAMON",
|
||||
.size = 0x0100000,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.mask_flags = MTD_WRITEABLE
|
||||
},{
|
||||
.name = "raw kernel",
|
||||
.size = (0x300000 - 0x40000), /* last 256KB is yamon env */
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}
|
||||
};
|
||||
|
||||
static struct mtd_info *mymtd;
|
||||
|
||||
static int __init alchemy_mtd_init(void)
|
||||
{
|
||||
struct mtd_partition *parts;
|
||||
int nb_parts = 0;
|
||||
unsigned long window_addr;
|
||||
unsigned long window_size;
|
||||
|
||||
/* Default flash buswidth */
|
||||
alchemy_map.bankwidth = BOARD_FLASH_WIDTH;
|
||||
|
||||
window_addr = 0x20000000 - BOARD_FLASH_SIZE;
|
||||
window_size = BOARD_FLASH_SIZE;
|
||||
|
||||
/*
|
||||
* Static partition definition selection
|
||||
*/
|
||||
parts = alchemy_partitions;
|
||||
nb_parts = ARRAY_SIZE(alchemy_partitions);
|
||||
alchemy_map.size = window_size;
|
||||
|
||||
/*
|
||||
* Now let's probe for the actual flash. Do it here since
|
||||
* specific machine settings might have been set above.
|
||||
*/
|
||||
printk(KERN_NOTICE BOARD_MAP_NAME ": probing %d-bit flash bus\n",
|
||||
alchemy_map.bankwidth*8);
|
||||
alchemy_map.virt = ioremap(window_addr, window_size);
|
||||
mymtd = do_map_probe("cfi_probe", &alchemy_map);
|
||||
if (!mymtd) {
|
||||
iounmap(alchemy_map.virt);
|
||||
return -ENXIO;
|
||||
}
|
||||
mymtd->owner = THIS_MODULE;
|
||||
|
||||
add_mtd_partitions(mymtd, parts, nb_parts);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit alchemy_mtd_cleanup(void)
|
||||
{
|
||||
if (mymtd) {
|
||||
del_mtd_partitions(mymtd);
|
||||
map_destroy(mymtd);
|
||||
iounmap(alchemy_map.virt);
|
||||
}
|
||||
}
|
||||
|
||||
module_init(alchemy_mtd_init);
|
||||
module_exit(alchemy_mtd_cleanup);
|
||||
|
||||
MODULE_AUTHOR("Embedded Alley Solutions, Inc");
|
||||
MODULE_DESCRIPTION(BOARD_MAP_NAME " MTD driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -457,10 +457,10 @@ config MTD_NAND_NOMADIK
|
|||
|
||||
config MTD_NAND_SH_FLCTL
|
||||
tristate "Support for NAND on Renesas SuperH FLCTL"
|
||||
depends on MTD_NAND && SUPERH && CPU_SUBTYPE_SH7723
|
||||
depends on MTD_NAND && SUPERH
|
||||
help
|
||||
Several Renesas SuperH CPU has FLCTL. This option enables support
|
||||
for NAND Flash using FLCTL. This driver support SH7723.
|
||||
for NAND Flash using FLCTL.
|
||||
|
||||
config MTD_NAND_DAVINCI
|
||||
tristate "Support NAND on DaVinci SoC"
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <asm/io.h>
|
||||
|
||||
#include <asm/mach-au1x00/au1xxx.h>
|
||||
#include <asm/mach-db1x00/bcsr.h>
|
||||
|
||||
/*
|
||||
* MTD structure for NAND controller
|
||||
|
|
@ -475,7 +476,8 @@ static int __init au1xxx_nand_init(void)
|
|||
/* set gpio206 high */
|
||||
au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
|
||||
|
||||
boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1);
|
||||
boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
|
||||
|
||||
switch (boot_swapboot) {
|
||||
case 0:
|
||||
case 2:
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/*
|
||||
* SuperH FLCTL nand controller
|
||||
*
|
||||
* Copyright © 2008 Renesas Solutions Corp.
|
||||
* Copyright © 2008 Atom Create Engineering Co., Ltd.
|
||||
* Copyright (c) 2008 Renesas Solutions Corp.
|
||||
* Copyright (c) 2008 Atom Create Engineering Co., Ltd.
|
||||
*
|
||||
* Based on fsl_elbc_nand.c, Copyright © 2006-2007 Freescale Semiconductor
|
||||
* Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -75,6 +75,11 @@ static void start_translation(struct sh_flctl *flctl)
|
|||
writeb(TRSTRT, FLTRCR(flctl));
|
||||
}
|
||||
|
||||
static void timeout_error(struct sh_flctl *flctl, const char *str)
|
||||
{
|
||||
dev_err(&flctl->pdev->dev, "Timeout occured in %s\n", str);
|
||||
}
|
||||
|
||||
static void wait_completion(struct sh_flctl *flctl)
|
||||
{
|
||||
uint32_t timeout = LOOP_TIMEOUT_MAX;
|
||||
|
|
@ -87,7 +92,7 @@ static void wait_completion(struct sh_flctl *flctl)
|
|||
udelay(1);
|
||||
}
|
||||
|
||||
printk(KERN_ERR "wait_completion(): Timeout occured \n");
|
||||
timeout_error(flctl, __func__);
|
||||
writeb(0x0, FLTRCR(flctl));
|
||||
}
|
||||
|
||||
|
|
@ -100,6 +105,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr)
|
|||
addr = page_addr; /* ERASE1 */
|
||||
} else if (page_addr != -1) {
|
||||
/* SEQIN, READ0, etc.. */
|
||||
if (flctl->chip.options & NAND_BUSWIDTH_16)
|
||||
column >>= 1;
|
||||
if (flctl->page_size) {
|
||||
addr = column & 0x0FFF;
|
||||
addr |= (page_addr & 0xff) << 16;
|
||||
|
|
@ -132,7 +139,7 @@ static void wait_rfifo_ready(struct sh_flctl *flctl)
|
|||
return;
|
||||
udelay(1);
|
||||
}
|
||||
printk(KERN_ERR "wait_rfifo_ready(): Timeout occured \n");
|
||||
timeout_error(flctl, __func__);
|
||||
}
|
||||
|
||||
static void wait_wfifo_ready(struct sh_flctl *flctl)
|
||||
|
|
@ -146,7 +153,7 @@ static void wait_wfifo_ready(struct sh_flctl *flctl)
|
|||
return;
|
||||
udelay(1);
|
||||
}
|
||||
printk(KERN_ERR "wait_wfifo_ready(): Timeout occured \n");
|
||||
timeout_error(flctl, __func__);
|
||||
}
|
||||
|
||||
static int wait_recfifo_ready(struct sh_flctl *flctl, int sector_number)
|
||||
|
|
@ -198,7 +205,7 @@ static int wait_recfifo_ready(struct sh_flctl *flctl, int sector_number)
|
|||
writel(0, FL4ECCCR(flctl));
|
||||
}
|
||||
|
||||
printk(KERN_ERR "wait_recfifo_ready(): Timeout occured \n");
|
||||
timeout_error(flctl, __func__);
|
||||
return 1; /* timeout */
|
||||
}
|
||||
|
||||
|
|
@ -214,7 +221,7 @@ static void wait_wecfifo_ready(struct sh_flctl *flctl)
|
|||
return;
|
||||
udelay(1);
|
||||
}
|
||||
printk(KERN_ERR "wait_wecfifo_ready(): Timeout occured \n");
|
||||
timeout_error(flctl, __func__);
|
||||
}
|
||||
|
||||
static void read_datareg(struct sh_flctl *flctl, int offset)
|
||||
|
|
@ -275,7 +282,7 @@ static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
|
|||
static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
|
||||
{
|
||||
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
||||
uint32_t flcmncr_val = readl(FLCMNCR(flctl));
|
||||
uint32_t flcmncr_val = readl(FLCMNCR(flctl)) & ~SEL_16BIT;
|
||||
uint32_t flcmdcr_val, addr_len_bytes = 0;
|
||||
|
||||
/* Set SNAND bit if page size is 2048byte */
|
||||
|
|
@ -297,6 +304,8 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va
|
|||
case NAND_CMD_READOOB:
|
||||
addr_len_bytes = flctl->rw_ADRCNT;
|
||||
flcmdcr_val |= CDSRC_E;
|
||||
if (flctl->chip.options & NAND_BUSWIDTH_16)
|
||||
flcmncr_val |= SEL_16BIT;
|
||||
break;
|
||||
case NAND_CMD_SEQIN:
|
||||
/* This case is that cmd is READ0 or READ1 or READ00 */
|
||||
|
|
@ -305,6 +314,8 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va
|
|||
case NAND_CMD_PAGEPROG:
|
||||
addr_len_bytes = flctl->rw_ADRCNT;
|
||||
flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW;
|
||||
if (flctl->chip.options & NAND_BUSWIDTH_16)
|
||||
flcmncr_val |= SEL_16BIT;
|
||||
break;
|
||||
case NAND_CMD_READID:
|
||||
flcmncr_val &= ~SNAND_E;
|
||||
|
|
@ -523,6 +534,8 @@ static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
|
|||
set_addr(mtd, 0, page_addr);
|
||||
|
||||
flctl->read_bytes = mtd->writesize + mtd->oobsize;
|
||||
if (flctl->chip.options & NAND_BUSWIDTH_16)
|
||||
column >>= 1;
|
||||
flctl->index += column;
|
||||
goto read_normal_exit;
|
||||
|
||||
|
|
@ -686,6 +699,18 @@ static uint8_t flctl_read_byte(struct mtd_info *mtd)
|
|||
return data;
|
||||
}
|
||||
|
||||
static uint16_t flctl_read_word(struct mtd_info *mtd)
|
||||
{
|
||||
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
||||
int index = flctl->index;
|
||||
uint16_t data;
|
||||
uint16_t *buf = (uint16_t *)&flctl->done_buff[index];
|
||||
|
||||
data = *buf;
|
||||
flctl->index += 2;
|
||||
return data;
|
||||
}
|
||||
|
||||
static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -769,38 +794,36 @@ static int flctl_chip_init_tail(struct mtd_info *mtd)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int __init flctl_probe(struct platform_device *pdev)
|
||||
static int __devinit flctl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct sh_flctl *flctl;
|
||||
struct mtd_info *flctl_mtd;
|
||||
struct nand_chip *nand;
|
||||
struct sh_flctl_platform_data *pdata;
|
||||
int ret;
|
||||
int ret = -ENXIO;
|
||||
|
||||
pdata = pdev->dev.platform_data;
|
||||
if (pdata == NULL) {
|
||||
printk(KERN_ERR "sh_flctl platform_data not found.\n");
|
||||
return -ENODEV;
|
||||
dev_err(&pdev->dev, "no platform data defined\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
flctl = kzalloc(sizeof(struct sh_flctl), GFP_KERNEL);
|
||||
if (!flctl) {
|
||||
printk(KERN_ERR "Unable to allocate NAND MTD dev structure.\n");
|
||||
dev_err(&pdev->dev, "failed to allocate driver data\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
printk(KERN_ERR "%s: resource not found.\n", __func__);
|
||||
ret = -ENODEV;
|
||||
dev_err(&pdev->dev, "failed to get I/O memory\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
flctl->reg = ioremap(res->start, res->end - res->start + 1);
|
||||
flctl->reg = ioremap(res->start, resource_size(res));
|
||||
if (flctl->reg == NULL) {
|
||||
printk(KERN_ERR "%s: ioremap error.\n", __func__);
|
||||
ret = -ENOMEM;
|
||||
dev_err(&pdev->dev, "failed to remap I/O memory\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
|
|
@ -808,6 +831,7 @@ static int __init flctl_probe(struct platform_device *pdev)
|
|||
flctl_mtd = &flctl->mtd;
|
||||
nand = &flctl->chip;
|
||||
flctl_mtd->priv = nand;
|
||||
flctl->pdev = pdev;
|
||||
flctl->hwecc = pdata->has_hwecc;
|
||||
|
||||
flctl_register_init(flctl, pdata->flcmncr_val);
|
||||
|
|
@ -825,6 +849,11 @@ static int __init flctl_probe(struct platform_device *pdev)
|
|||
nand->select_chip = flctl_select_chip;
|
||||
nand->cmdfunc = flctl_cmdfunc;
|
||||
|
||||
if (pdata->flcmncr_val & SEL_16BIT) {
|
||||
nand->options |= NAND_BUSWIDTH_16;
|
||||
nand->read_word = flctl_read_word;
|
||||
}
|
||||
|
||||
ret = nand_scan_ident(flctl_mtd, 1);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
|
@ -846,7 +875,7 @@ err:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int __exit flctl_remove(struct platform_device *pdev)
|
||||
static int __devexit flctl_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_flctl *flctl = platform_get_drvdata(pdev);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue