diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt
index e2f744b3e9cb..719ef66a1c15 100644
--- a/bindings/pci/pci-msm.txt
+++ b/bindings/pci/pci-msm.txt
@@ -585,3 +585,53 @@ Example
 			qcom,iommu-cfg = <0x3> /* SMMU PRESENT. SET S1 BYPASS */
 			qcom,iommu-range = <0x0 0x10000000 0x0 0x40000000>;
 		};
+
+==============
+i2c child node
+==============
+
+- compatible:
+	Usage: required
+	Value type: <stringlist>
+	Definition: Compatible list, contains
+		- "qcom,pcie0-i2c-ntn3" for NTN3 switch attached to Root port 0
+
+- reg:
+	Usage: required
+	Value type: <u16>
+	Definition: i2c slave id
+
+- gpio-config-reg:
+	Usage: optional
+	Value type: <u32>
+	Definition: Slave GPIO configuration register address
+
+- ep-reset-reg:
+	Usage: optional
+	Value type: <u32>
+	Definition: Slave endpoint reset register address
+
+- ep-reset-gpio-mask:
+	Usage: optional
+	Value type: <u32>
+	Definition: Slave GPIO number as 32-bit mask
+
+- dump-regs:
+	Usage: optional
+	Value Type: Array of <u32>
+	Definition: List of slave registers to dump by i2c read
+
+=======
+Example
+=======
+
+&i2c_3 {
+	pcie_i2c_ctrl: pcie_i2c_ctrl {
+		compatible = "qcom,pcie0-i2c-ntn3";
+		reg = <0x77>;
+		gpio-config-reg = <0x801208>;
+		ep-reset-reg = <0x801210>;
+		ep-reset-gpio-mask = <0xf>;
+		dump-regs = <0x801330 0x801350 0x801370>;
+	};
+};