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arm: mvebu: add L2 cache support

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Signed-off-by: Gregory CLEMENT <[email protected]>
Tested-and-reviewed-by: Yehuda Yitschak <[email protected]>
Tested-and-reviewed-by: Lior Amsalem <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>

Cc: Jason Cooper <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Olof Johansson <[email protected]>
Signed-off-by: Jason Cooper <[email protected]>
This commit is contained in:
Gregory CLEMENT 2012-09-26 18:02:48 +02:00 • committed by Jason Cooper
commit d792b1e94d
2 changed files with 5 additions and 0 deletions
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1
arch/arm/mach-mvebu/Kconfig
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@ -22,6 +22,7 @@ config MACH_ARMADA_370_XP
bool
select ARMADA_370_XP_TIMER
select HAVE_SMP
select CACHE_L2X0
select CPU_PJ4B
config MACH_ARMADA_370

4
arch/arm/mach-mvebu/irq-armada-370-xp.c
View file

@ -25,6 +25,7 @@
#include <asm/mach/arch.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
#include <asm/hardware/cache-l2x0.h>
/* Interrupt Controller Registers Map */
#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
@ -210,4 +211,7 @@ static const struct of_device_id mpic_of_match[] __initconst = {
void __init armada_370_xp_init_irq(void)
{
of_irq_init(mpic_of_match);
#ifdef CONFIG_CACHE_L2X0
l2x0_of_init(0, ~0UL);
#endif
}