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clk: qcom: Fix sdc 144kHz frequency entry

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The pre-divider for the sdc clocks only has 2 bits in it, so we
can't possibly divide by anything larger than 4 here.
Furthermore, we program the value of ~(n - m) and the n value is
larger than 8 bits (max of 256). Replace this entry with 200kHz
which is close enough to 144kHz to be usable.

Cc: Kumar Gala <[email protected]>
Cc: Andy Gross <[email protected]>
Fixes: 24d8fba44a "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
This commit is contained in:
Stephen Boyd 2014-08-29 12:49:26 -07:00 • committed by Mike Turquette
commit d8210e28e5
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/qcom/gcc-ipq806x.c
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@ -1095,7 +1095,7 @@ static struct clk_branch prng_clk = {
};
static const struct freq_tbl clk_tbl_sdc[] = {
{ 144000, P_PXO, 5, 18,625 },
{ 200000, P_PXO, 2, 2, 125 },
{ 400000, P_PLL8, 4, 1, 240 },
{ 16000000, P_PLL8, 4, 1, 6 },
{ 17070000, P_PLL8, 1, 2, 45 },