From d67ee519eeca3b389f1540b7d96b4f66297cf439 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Fri, 8 Jan 2021 10:26:06 +0800 Subject: [PATCH] firmware: qcom_scm: Add calls to support MSS restart Add SCM calls to support MSS restart for pil modem. Change-Id: Ic2a62ca9371f299fd750cbff28443b9e67751f8a Signed-off-by: Lijuan Gao --- drivers/firmware/qcom_scm.c | 20 +++++++++++++++++++- include/linux/qcom_scm.h | 4 +++- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 48323ddfff3d..5c4c4e8288a6 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2010,2015,2020 The Linux Foundation. All rights reserved. +/* Copyright (c) 2010,2015,2020-2021 The Linux Foundation. All rights reserved. * Copyright (C) 2015 Linaro Ltd. */ #include @@ -264,6 +264,24 @@ int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size) } EXPORT_SYMBOL(qcom_scm_pas_mem_setup); +/** + * qcom_scm_pas_mss_reset() - MSS restart + */ +int qcom_scm_pas_mss_reset(bool reset) +{ + int ret; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = __qcom_scm_pas_mss_reset(__scm->dev, reset); + qcom_scm_clk_disable(); + + return ret; +} +EXPORT_SYMBOL(qcom_scm_pas_mss_reset); + /** * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware * and reset the remote processor diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index cf2519efb7b4..d87a296c9f40 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2010-2015, 2018-2020 The Linux Foundation. All rights reserved. +/* Copyright (c) 2010-2015, 2018-2021 The Linux Foundation. All rights reserved. * Copyright (C) 2015 Linaro Ltd. */ #ifndef __QCOM_SCM_H @@ -95,6 +95,7 @@ extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size); extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size); +extern int qcom_scm_pas_mss_reset(bool reset); extern int qcom_scm_pas_auth_and_reset(u32 peripheral); extern int qcom_scm_pas_shutdown(u32 peripheral); extern int qcom_scm_get_sec_dump_state(u32 *dump_state); @@ -223,6 +224,7 @@ static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size) { return -ENODEV; } static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size) { return -ENODEV; } +static inline int qcom_scm_pas_mss_reset(bool reset) { return -ENODEV; } static inline int qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; } static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }