mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull RAS updates from Ingo Molnar:
"Various RAS updates:
- AMD MCE support updates for future CPUs, fixes and 'SMCA' (Scalable
MCA) error decoding support (Aravind Gopalakrishnan)
- x86 memcpy_mcsafe() support, to enable smart(er) hardware error
recovery in NVDIMM drivers, based on an extension of the x86
exception handling code. (Tony Luck)"
* 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
EDAC/sb_edac: Fix computation of channel address
x86/mm, x86/mce: Add memcpy_mcsafe()
x86/mce/AMD: Document some functionality
x86/mce: Clarify comments regarding deferred error
x86/mce/AMD: Fix logic to obtain block address
x86/mce/AMD, EDAC: Enable error decoding of Scalable MCA errors
x86/mce: Move MCx_CONFIG MSR definitions
x86/mce: Check for faults tagged in EXTABLE_CLASS_FAULT exception table entries
x86/mm: Expand the exception table logic to allow new handling options
x86/mce/AMD: Set MCAX Enable bit
x86/mce/AMD: Carve out threshold block preparation
x86/mce/AMD: Fix LVT offset configuration for thresholding
x86/mce/AMD: Reduce number of blocks scanned per bank
x86/mce/AMD: Do not perform shared bank check for future processors
x86/mce: Fix order of AMD MCE init function call
This commit is contained in:
Linus Torvalds
commit
d88bfe1d68
18 changed files with 962 additions and 184 deletions
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|
@ -147,6 +147,135 @@ static const char * const mc6_mce_desc[] = {
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"Status Register File",
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};
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/* Scalable MCA error strings */
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static const char * const f17h_ls_mce_desc[] = {
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"Load queue parity",
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"Store queue parity",
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"Miss address buffer payload parity",
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"L1 TLB parity",
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"", /* reserved */
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"DC tag error type 6",
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"DC tag error type 1",
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"Internal error type 1",
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"Internal error type 2",
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"Sys Read data error thread 0",
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"Sys read data error thread 1",
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"DC tag error type 2",
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"DC data error type 1 (poison comsumption)",
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"DC data error type 2",
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"DC data error type 3",
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"DC tag error type 4",
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"L2 TLB parity",
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"PDC parity error",
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"DC tag error type 3",
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"DC tag error type 5",
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"L2 fill data error",
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};
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static const char * const f17h_if_mce_desc[] = {
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"microtag probe port parity error",
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"IC microtag or full tag multi-hit error",
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"IC full tag parity",
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"IC data array parity",
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"Decoupling queue phys addr parity error",
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"L0 ITLB parity error",
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"L1 ITLB parity error",
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"L2 ITLB parity error",
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"BPQ snoop parity on Thread 0",
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"BPQ snoop parity on Thread 1",
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"L1 BTB multi-match error",
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"L2 BTB multi-match error",
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};
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static const char * const f17h_l2_mce_desc[] = {
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"L2M tag multi-way-hit error",
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"L2M tag ECC error",
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"L2M data ECC error",
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"HW assert",
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};
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static const char * const f17h_de_mce_desc[] = {
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"uop cache tag parity error",
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"uop cache data parity error",
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"Insn buffer parity error",
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"Insn dispatch queue parity error",
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"Fetch address FIFO parity",
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"Patch RAM data parity",
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"Patch RAM sequencer parity",
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"uop buffer parity"
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};
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static const char * const f17h_ex_mce_desc[] = {
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"Watchdog timeout error",
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"Phy register file parity",
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"Flag register file parity",
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"Immediate displacement register file parity",
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"Address generator payload parity",
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"EX payload parity",
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"Checkpoint queue parity",
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"Retire dispatch queue parity",
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};
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static const char * const f17h_fp_mce_desc[] = {
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"Physical register file parity",
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"Freelist parity error",
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"Schedule queue parity",
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"NSQ parity error",
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"Retire queue parity",
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"Status register file parity",
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};
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static const char * const f17h_l3_mce_desc[] = {
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"Shadow tag macro ECC error",
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"Shadow tag macro multi-way-hit error",
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"L3M tag ECC error",
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"L3M tag multi-way-hit error",
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"L3M data ECC error",
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"XI parity, L3 fill done channel error",
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"L3 victim queue parity",
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"L3 HW assert",
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};
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static const char * const f17h_cs_mce_desc[] = {
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"Illegal request from transport layer",
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"Address violation",
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"Security violation",
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"Illegal response from transport layer",
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"Unexpected response",
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"Parity error on incoming request or probe response data",
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"Parity error on incoming read response data",
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"Atomic request parity",
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"ECC error on probe filter access",
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};
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static const char * const f17h_pie_mce_desc[] = {
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"HW assert",
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"Internal PIE register security violation",
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"Error on GMI link",
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"Poison data written to internal PIE register",
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};
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static const char * const f17h_umc_mce_desc[] = {
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"DRAM ECC error",
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"Data poison error on DRAM",
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"SDP parity error",
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"Advanced peripheral bus error",
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"Command/address parity error",
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"Write data CRC error",
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};
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static const char * const f17h_pb_mce_desc[] = {
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"Parameter Block RAM ECC error",
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};
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static const char * const f17h_psp_mce_desc[] = {
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"PSP RAM ECC or parity error",
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};
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static const char * const f17h_smu_mce_desc[] = {
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"SMU RAM ECC or parity error",
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};
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static bool f12h_mc0_mce(u16 ec, u8 xec)
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{
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bool ret = false;
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@ -691,6 +820,177 @@ static void decode_mc6_mce(struct mce *m)
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pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
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}
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static void decode_f17h_core_errors(const char *ip_name, u8 xec,
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unsigned int mca_type)
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{
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const char * const *error_desc_array;
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size_t len;
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pr_emerg(HW_ERR "%s Error: ", ip_name);
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switch (mca_type) {
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case SMCA_LS:
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error_desc_array = f17h_ls_mce_desc;
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len = ARRAY_SIZE(f17h_ls_mce_desc) - 1;
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if (xec == 0x4) {
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pr_cont("Unrecognized LS MCA error code.\n");
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return;
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}
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break;
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case SMCA_IF:
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error_desc_array = f17h_if_mce_desc;
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len = ARRAY_SIZE(f17h_if_mce_desc) - 1;
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break;
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case SMCA_L2_CACHE:
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error_desc_array = f17h_l2_mce_desc;
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len = ARRAY_SIZE(f17h_l2_mce_desc) - 1;
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break;
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case SMCA_DE:
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error_desc_array = f17h_de_mce_desc;
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len = ARRAY_SIZE(f17h_de_mce_desc) - 1;
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break;
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case SMCA_EX:
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error_desc_array = f17h_ex_mce_desc;
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len = ARRAY_SIZE(f17h_ex_mce_desc) - 1;
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break;
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case SMCA_FP:
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error_desc_array = f17h_fp_mce_desc;
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len = ARRAY_SIZE(f17h_fp_mce_desc) - 1;
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break;
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case SMCA_L3_CACHE:
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error_desc_array = f17h_l3_mce_desc;
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len = ARRAY_SIZE(f17h_l3_mce_desc) - 1;
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break;
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default:
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pr_cont("Corrupted MCA core error info.\n");
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return;
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}
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if (xec > len) {
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pr_cont("Unrecognized %s MCA bank error code.\n",
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amd_core_mcablock_names[mca_type]);
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return;
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}
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pr_cont("%s.\n", error_desc_array[xec]);
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}
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static void decode_df_errors(u8 xec, unsigned int mca_type)
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{
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const char * const *error_desc_array;
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size_t len;
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pr_emerg(HW_ERR "Data Fabric Error: ");
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switch (mca_type) {
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case SMCA_CS:
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error_desc_array = f17h_cs_mce_desc;
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len = ARRAY_SIZE(f17h_cs_mce_desc) - 1;
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break;
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case SMCA_PIE:
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error_desc_array = f17h_pie_mce_desc;
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len = ARRAY_SIZE(f17h_pie_mce_desc) - 1;
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break;
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default:
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pr_cont("Corrupted MCA Data Fabric info.\n");
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return;
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}
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if (xec > len) {
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pr_cont("Unrecognized %s MCA bank error code.\n",
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amd_df_mcablock_names[mca_type]);
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return;
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}
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pr_cont("%s.\n", error_desc_array[xec]);
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}
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/* Decode errors according to Scalable MCA specification */
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static void decode_smca_errors(struct mce *m)
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{
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u32 addr = MSR_AMD64_SMCA_MCx_IPID(m->bank);
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unsigned int hwid, mca_type, i;
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u8 xec = XEC(m->status, xec_mask);
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const char * const *error_desc_array;
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const char *ip_name;
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u32 low, high;
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size_t len;
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if (rdmsr_safe(addr, &low, &high)) {
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pr_emerg("Invalid IP block specified, error information is unreliable.\n");
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return;
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}
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hwid = high & MCI_IPID_HWID;
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mca_type = (high & MCI_IPID_MCATYPE) >> 16;
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pr_emerg(HW_ERR "MC%d IPID value: 0x%08x%08x\n", m->bank, high, low);
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/*
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* Based on hwid and mca_type values, decode errors from respective IPs.
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* Note: mca_type values make sense only in the context of an hwid.
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*/
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for (i = 0; i < ARRAY_SIZE(amd_hwids); i++)
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if (amd_hwids[i].hwid == hwid)
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break;
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switch (i) {
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case SMCA_F17H_CORE:
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ip_name = (mca_type == SMCA_L3_CACHE) ?
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"L3 Cache" : "F17h Core";
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return decode_f17h_core_errors(ip_name, xec, mca_type);
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break;
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case SMCA_DF:
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return decode_df_errors(xec, mca_type);
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break;
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case SMCA_UMC:
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error_desc_array = f17h_umc_mce_desc;
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len = ARRAY_SIZE(f17h_umc_mce_desc) - 1;
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break;
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case SMCA_PB:
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error_desc_array = f17h_pb_mce_desc;
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len = ARRAY_SIZE(f17h_pb_mce_desc) - 1;
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break;
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|
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case SMCA_PSP:
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error_desc_array = f17h_psp_mce_desc;
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len = ARRAY_SIZE(f17h_psp_mce_desc) - 1;
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break;
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|
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case SMCA_SMU:
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error_desc_array = f17h_smu_mce_desc;
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len = ARRAY_SIZE(f17h_smu_mce_desc) - 1;
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break;
|
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|
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default:
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pr_emerg(HW_ERR "HWID:%d does not match any existing IPs.\n", hwid);
|
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return;
|
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}
|
||||
|
||||
ip_name = amd_hwids[i].name;
|
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pr_emerg(HW_ERR "%s Error: ", ip_name);
|
||||
|
||||
if (xec > len) {
|
||||
pr_cont("Unrecognized %s MCA bank error code.\n", ip_name);
|
||||
return;
|
||||
}
|
||||
|
||||
pr_cont("%s.\n", error_desc_array[xec]);
|
||||
}
|
||||
|
||||
static inline void amd_decode_err_code(u16 ec)
|
||||
{
|
||||
if (INT_ERROR(ec)) {
|
||||
|
|
@ -752,6 +1052,7 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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|||
struct mce *m = (struct mce *)data;
|
||||
struct cpuinfo_x86 *c = &cpu_data(m->extcpu);
|
||||
int ecc;
|
||||
u32 ebx = cpuid_ebx(0x80000007);
|
||||
|
||||
if (amd_filter_mce(m))
|
||||
return NOTIFY_STOP;
|
||||
|
|
@ -769,11 +1070,20 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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|||
((m->status & MCI_STATUS_PCC) ? "PCC" : "-"),
|
||||
((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
|
||||
|
||||
if (c->x86 == 0x15 || c->x86 == 0x16)
|
||||
if (c->x86 >= 0x15)
|
||||
pr_cont("|%s|%s",
|
||||
((m->status & MCI_STATUS_DEFERRED) ? "Deferred" : "-"),
|
||||
((m->status & MCI_STATUS_POISON) ? "Poison" : "-"));
|
||||
|
||||
if (!!(ebx & BIT(3))) {
|
||||
u32 low, high;
|
||||
u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
|
||||
|
||||
if (!rdmsr_safe(addr, &low, &high) &&
|
||||
(low & MCI_CONFIG_MCAX))
|
||||
pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
|
||||
}
|
||||
|
||||
/* do the two bits[14:13] together */
|
||||
ecc = (m->status >> 45) & 0x3;
|
||||
if (ecc)
|
||||
|
|
@ -784,6 +1094,11 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
|
|||
if (m->status & MCI_STATUS_ADDRV)
|
||||
pr_emerg(HW_ERR "MC%d Error Address: 0x%016llx\n", m->bank, m->addr);
|
||||
|
||||
if (!!(ebx & BIT(3))) {
|
||||
decode_smca_errors(m);
|
||||
goto err_code;
|
||||
}
|
||||
|
||||
if (!fam_ops)
|
||||
goto err_code;
|
||||
|
||||
|
|
@ -834,6 +1149,7 @@ static struct notifier_block amd_mce_dec_nb = {
|
|||
static int __init mce_amd_init(void)
|
||||
{
|
||||
struct cpuinfo_x86 *c = &boot_cpu_data;
|
||||
u32 ebx;
|
||||
|
||||
if (c->x86_vendor != X86_VENDOR_AMD)
|
||||
return -ENODEV;
|
||||
|
|
@ -888,10 +1204,18 @@ static int __init mce_amd_init(void)
|
|||
fam_ops->mc2_mce = f16h_mc2_mce;
|
||||
break;
|
||||
|
||||
case 0x17:
|
||||
ebx = cpuid_ebx(0x80000007);
|
||||
xec_mask = 0x3f;
|
||||
if (!(ebx & BIT(3))) {
|
||||
printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");
|
||||
goto err_out;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
|
||||
kfree(fam_ops);
|
||||
fam_ops = NULL;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
pr_info("MCE: In-kernel MCE decoding enabled.\n");
|
||||
|
|
@ -899,6 +1223,11 @@ static int __init mce_amd_init(void)
|
|||
mce_register_decode_chain(&amd_mce_dec_nb);
|
||||
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
kfree(fam_ops);
|
||||
fam_ops = NULL;
|
||||
return -EINVAL;
|
||||
}
|
||||
early_initcall(mce_amd_init);
|
||||
|
||||
|
|
|
|||
|
|
@ -1839,8 +1839,8 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
|
|||
edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
|
||||
n_tads, gb, (mb*1000)/1024,
|
||||
((u64)tmp_mb) << 20L,
|
||||
(u32)TAD_SOCK(reg),
|
||||
(u32)TAD_CH(reg),
|
||||
(u32)(1 << TAD_SOCK(reg)),
|
||||
(u32)TAD_CH(reg) + 1,
|
||||
(u32)TAD_TGT0(reg),
|
||||
(u32)TAD_TGT1(reg),
|
||||
(u32)TAD_TGT2(reg),
|
||||
|
|
@ -2118,7 +2118,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
|
|||
}
|
||||
|
||||
ch_way = TAD_CH(reg) + 1;
|
||||
sck_way = TAD_SOCK(reg) + 1;
|
||||
sck_way = 1 << TAD_SOCK(reg);
|
||||
|
||||
if (ch_way == 3)
|
||||
idx = addr >> 6;
|
||||
|
|
@ -2175,7 +2175,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
|
|||
n_tads,
|
||||
addr,
|
||||
limit,
|
||||
(u32)TAD_SOCK(reg),
|
||||
sck_way,
|
||||
ch_way,
|
||||
offset,
|
||||
idx,
|
||||
|
|
@ -2190,18 +2190,12 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
|
|||
offset, addr);
|
||||
return -EINVAL;
|
||||
}
|
||||
addr -= offset;
|
||||
/* Store the low bits [0:6] of the addr */
|
||||
ch_addr = addr & 0x7f;
|
||||
/* Remove socket wayness and remove 6 bits */
|
||||
addr >>= 6;
|
||||
addr = div_u64(addr, sck_xch);
|
||||
#if 0
|
||||
/* Divide by channel way */
|
||||
addr = addr / ch_way;
|
||||
#endif
|
||||
/* Recover the last 6 bits */
|
||||
ch_addr |= addr << 6;
|
||||
|
||||
ch_addr = addr - offset;
|
||||
ch_addr >>= (6 + shiftup);
|
||||
ch_addr /= ch_way * sck_way;
|
||||
ch_addr <<= (6 + shiftup);
|
||||
ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
|
||||
|
||||
/*
|
||||
* Step 3) Decode rank
|
||||
|
|
|
|||
Loading…
Reference in a new issue