From d5836468bf44847f27955f2f67c00950d466c345 Mon Sep 17 00:00:00 2001
From: Elliot Berman <eberman@quicinc.com>
Date: Mon, 5 Aug 2019 15:17:56 -0700
Subject: [PATCH 1/2] bindings: Add qcom,msm-hang-detect schema

Added msm_hang_detect.yaml by converting msm_hang_detect.txt from
commit <baa63fa212bd> (Merge "ARM: dts: msm: Add multiple refresh
rates for sw43404").

Change-Id: I7225fdc5915b9fbda69cc5b85fc4c2ff4d5750f7
---
 bindings/arm/msm/msm_hang_detect.yaml | 76 +++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 bindings/arm/msm/msm_hang_detect.yaml

diff --git a/bindings/arm/msm/msm_hang_detect.yaml b/bindings/arm/msm/msm_hang_detect.yaml
new file mode 100644
index 000000000000..352bcb62021f
--- /dev/null
+++ b/bindings/arm/msm/msm_hang_detect.yaml
@@ -0,0 +1,76 @@
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/msm/msm_hang_detect.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: QTI MSM Core Hang Detection
+
+maintainers:
+  - Elliot Berman <eberman@quicinc.com>
+
+description: |
+  Core Hang Detection provides the three sysfs entries for configuring
+  threshold, PMU event mux select and to enable hang detection.
+
+  If core is hung for threshold time (value X 10ns) and no
+  heart beat event from pmu to core hang monitor detection, core hang
+  interrupt would be generated to reset the SOC via secure watchdog
+  to collect all cores context.
+
+  PMU event mux select can be programmed to one of the supported
+  events, for example-
+  1) Load Instruction executed,
+  2) Store Instructions executed
+  3) Instruction architecturally executed and etc.
+
+  Writing 1 into enable sysfs entry, enables core hang detection and
+  if there is no selected PMU mux event for 10ns core hang counter
+  gets incremented. Once counter reaches the programmed threshold value,
+  core hang interrupts generated to reset the SOC.
+
+properties:
+  compatible:
+    items:
+      -const: qcom,core-hang-detect
+
+  label:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: unique name used to create sysfs entry
+
+  qcom,threshold-arr:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      Array of APCS_ALIAS*_CORE_HANG_THRESHOLD register address
+      for each core.
+
+  qcom,config-arr:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      Array of APCS_ALIAS*_CORE_HANG_CONFIG register address
+      for each core.
+
+required:
+  - compatible
+  - label
+  - qcom,threshold-arr
+  - qcom,config-arr
+
+examples:
+  - |
+    For msm8937:
+    qcom,chd {
+      compatible = "qcom,core-hang-detect";
+      qcom,threshold-arr = <0xB088094 0xB098094 0xB0A8094
+        0xB0B8094 0xB188094 0xB198094 0xB1A8094 0xB1B8094>;
+      qcom,config-arr = <0xB08809C 0xB09809C 0xB0A809C
+        0xB0B809C 0xB18809C 0xB19809C 0xB1A809C 0xB1B809C>;
+    };
+
+    For msmtitanium:
+    qcom,chd {
+      compatible = "qcom,core-hang-detect";
+      qcom,threshold-arr = <0xB1880B0 0xB1980B0 0xB1A80B0
+        0xB1B80B0 0xB0880B0 0xB0980B0 0xB0A80B0 0xB0B80B0>;
+      qcom,config-arr = <0xB1880B8 0xB1980B8 0xB1A80B8
+        0xB1B80B8 0xB0880B8 0xB0980B8 0xB0A80B8 0xB0B80B8>;
+    };
\ No newline at end of file

From 647dd817cc06761ecb894fff5cdadee922097dde Mon Sep 17 00:00:00 2001
From: Elliot Berman <eberman@quicinc.com>
Date: Mon, 5 Aug 2019 15:19:13 -0700
Subject: [PATCH 2/2] ARM: dts: msm: Add core hang detection to dt

Add qcom,msm-hang-detect to device tree to enable MSM Core Hang
Detection on all cores.

Changed from 2 nodes (one for each of silver and gold) to 1 node because
that's semantically correct for the driver.

Change-Id: I10be3a765e20460f43ce4a8cb5e6580d99439f46
---
 qcom/lahaina.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index 066d44a8bd32..52b7b16cce7d 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -548,6 +548,15 @@
 		compatible = "qcom,secure-buffer";
 	};
 
+	qcom,chd {
+		compatible = "qcom,core-hang-detect";
+		label = "core";
+		qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058
+			0x18040058 0x18050058 0x18060058 0x18070058>;
+		qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060
+			0x18040060 0x18050060 0x18060060 0x18070060>;
+	};
+
 	aggre1_noc: interconnect@16e0000 {
 		compatible = "qcom,lahaina-aggre1_noc";
 		#interconnect-cells = <1>;