mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
This is the bulk of pin control changes for the v4.8 kernel cycle.
New drivers:
- New driver for Oxnas pin control and GPIO. This ARM-based chipset
is used in a few storage (NAS) type devices.
- New driver for the MAX77620/MAX20024 pin controller portions.
- New driver for the Intel Merrifield pin controller.
New subdrivers:
- New subdriver for the Qualcomm MDM9615
- New subdriver for the STM32F746 MCU
- New subdriver for the Broadcom NSP SoC.
Cleanups:
- Demodularization of bool compiled-in drivers.
Apart from this there is just regular incremental improvements to
a lot of drivers, especially Uniphier and PFC.
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Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.8 kernel cycle.
Nothing stands out as especially exiting: new drivers, new subdrivers,
lots of cleanups and incremental features.
Business as usual.
New drivers:
- New driver for Oxnas pin control and GPIO. This ARM-based chipset
is used in a few storage (NAS) type devices.
- New driver for the MAX77620/MAX20024 pin controller portions.
- New driver for the Intel Merrifield pin controller.
New subdrivers:
- New subdriver for the Qualcomm MDM9615
- New subdriver for the STM32F746 MCU
- New subdriver for the Broadcom NSP SoC.
Cleanups:
- Demodularization of bool compiled-in drivers.
Apart from this there is just regular incremental improvements to a
lot of drivers, especially Uniphier and PFC"
* tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits)
pinctrl: fix pincontrol definition for marvell
pinctrl: xway: fix typo
Revert "pinctrl: amd: make it explicitly non-modular"
pinctrl: iproc: Add NSP and Stingray GPIO support
pinctrl: Update iProc GPIO DT bindings
pinctrl: bcm: add OF dependencies
pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()
pinctrl: Add STM32F746 MCU support
pinctrl: intel: Protect set wake flow by spin lock
pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()
pinctrl: uniphier: add Ethernet pin-mux settings
sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code
pinctrl: ns2: fix return value check in ns2_pinmux_probe()
pinctrl: qcom: update DT bindings with ebi2 groups
pinctrl: qcom: establish proper EBI2 pin groups
pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro
Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
includes: dt-bindings: Add STM32F746 pinctrl DT bindings
pinctrl: sunxi: fix nand0 function name for sun8i
pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11
...
This commit is contained in:
Linus Torvalds
commit
d94ba9e7d8
119 changed files with 12550 additions and 2698 deletions
47
Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
Normal file
47
Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
* Oxford Semiconductor OXNAS SoC GPIO Controller
|
||||
|
||||
Please refer to gpio.txt for generic information regarding GPIO bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible: "oxsemi,ox810se-gpio"
|
||||
- reg: Base address and length for the device.
|
||||
- interrupts: The port interrupt shared by all pins.
|
||||
- gpio-controller: Marks the port as GPIO controller.
|
||||
- #gpio-cells: Two. The first cell is the pin number and
|
||||
the second cell is used to specify the gpio polarity as defined in
|
||||
defined in <dt-bindings/gpio/gpio.h>:
|
||||
0 = GPIO_ACTIVE_HIGH
|
||||
1 = GPIO_ACTIVE_LOW
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- #interrupt-cells: Two. The first cell is the GPIO number and second cell
|
||||
is used to specify the trigger type as defined in
|
||||
<dt-bindings/interrupt-controller/irq.h>:
|
||||
IRQ_TYPE_EDGE_RISING
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IRQ_TYPE_EDGE_FALLING
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||||
IRQ_TYPE_EDGE_BOTH
|
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- gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
|
||||
gpio base and count, should be in the format of numeric-gpio-range as
|
||||
specified in the gpio.txt file.
|
||||
|
||||
Example:
|
||||
|
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gpio0: gpio@0 {
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compatible = "oxsemi,ox810se-gpio";
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reg = <0x000000 0x100000>;
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interrupts = <21>;
|
||||
#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 32>;
|
||||
};
|
||||
|
||||
keys {
|
||||
...
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||||
|
||||
button-esc {
|
||||
label = "ESC";
|
||||
linux,code = <1>;
|
||||
gpios = <&gpio0 12 0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -3,8 +3,22 @@ Broadcom iProc GPIO/PINCONF Controller
|
|||
Required properties:
|
||||
|
||||
- compatible:
|
||||
Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio",
|
||||
"brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio"
|
||||
"brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
|
||||
supports full-featured pinctrl and GPIO functions used in various iProc
|
||||
based SoCs
|
||||
|
||||
May contain an SoC-specific compatibility string to accommodate any
|
||||
SoC-specific features
|
||||
|
||||
"brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
|
||||
"brcm,cygnus-crmu-gpio" for Cygnus SoCs
|
||||
|
||||
"brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
|
||||
disabled
|
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|
||||
"brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
|
||||
pinctrl support completely disabled in this IP block. In Stingray, a
|
||||
different IP block is used to handle pinctrl related functions
|
||||
|
||||
- reg:
|
||||
Define the base and range of the I/O address space that contains SoC
|
||||
|
|
|
|||
|
|
@ -0,0 +1,79 @@
|
|||
Broadcom NSP (Northstar plus) IOMUX Controller
|
||||
|
||||
The NSP IOMUX controller supports group based mux configuration. In
|
||||
addition, certain pins can be muxed to GPIO function individually.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Must be "brcm,nsp-pinmux"
|
||||
|
||||
- reg:
|
||||
Should contain the register physical address and length for each of
|
||||
GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers
|
||||
|
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Properties in subnodes:
|
||||
- function:
|
||||
The mux function to select
|
||||
|
||||
- groups:
|
||||
The list of groups to select with a given function
|
||||
|
||||
For more details, refer to
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
For example:
|
||||
|
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pinmux: pinmux@1803f1c0 {
|
||||
compatible = "brcm,nsp-pinmux";
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reg = <0x1803f1c0 0x04>,
|
||||
<0x18030028 0x04>,
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||||
<0x1803f408 0x04>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm &gpio_b &nand_sel>;
|
||||
|
||||
pwm: pwm {
|
||||
function = "pwm";
|
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groups = "pwm0_grp", "pwm1_grp";
|
||||
};
|
||||
|
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gpio_b: gpio_b {
|
||||
function = "gpio_b";
|
||||
groups = "gpio_b_0_grp", "gpio_b_1_grp";
|
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};
|
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|
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nand_sel: nand_sel {
|
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function = "nand";
|
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groups = "nand_grp";
|
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};
|
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};
|
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|
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List of supported functions and groups in Northstar Plus:
|
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|
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"spi": "spi_grp"
|
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|
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"i2c": "i2c_grp"
|
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|
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"mdio": "mdio_grp"
|
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|
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"pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"
|
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|
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"gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp"
|
||||
|
||||
"uart1": "uart1_grp"
|
||||
|
||||
"uart2": "uart2_grp"
|
||||
|
||||
"synce": "synce_grp"
|
||||
|
||||
"sata_led_grps": "sata0_led_grp", "sata1_led_grp"
|
||||
|
||||
"xtal_out": "xtal_out_grp"
|
||||
|
||||
"sdio": "sdio_pwr_grp", "sdio_1p8v_grp"
|
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|
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"switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp"
|
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|
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"nand": "nand_grp"
|
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|
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"emmc": "emmc_grp"
|
||||
57
Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt
Normal file
57
Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
* Oxford Semiconductor OXNAS SoC Family Pin Controller
|
||||
|
||||
Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
|
||||
../interrupt-controller/interrupts.txt for generic information regarding
|
||||
pin controller, GPIO, and interrupt bindings.
|
||||
|
||||
OXNAS 'pin configuration node' is a node of a group of pins which can be
|
||||
used for a specific device or function. This node represents configurations of
|
||||
pins, optional function, and optional mux related configuration.
|
||||
|
||||
Required properties for pin controller node:
|
||||
- compatible: "oxsemi,ox810se-pinctrl"
|
||||
- oxsemi,sys-ctrl: a phandle to the system controller syscon node
|
||||
|
||||
Required properties for pin configuration sub-nodes:
|
||||
- pins: List of pins to which the configuration applies.
|
||||
|
||||
Optional properties for pin configuration sub-nodes:
|
||||
----------------------------------------------------
|
||||
- function: Mux function for the specified pins.
|
||||
- bias-pull-up: Enable weak pull-up.
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "oxsemi,ox810se-pinctrl";
|
||||
|
||||
/* Regmap for sys registers */
|
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oxsemi,sys-ctrl = <&sys>;
|
||||
|
||||
pinctrl_uart2: pinctrl_uart2 {
|
||||
uart2a {
|
||||
pins = "gpio31";
|
||||
function = "fct3";
|
||||
};
|
||||
uart2b {
|
||||
pins = "gpio32";
|
||||
function = "fct3";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart2: serial@900000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x900000 0x100000>;
|
||||
clocks = <&sysclk>;
|
||||
interrupts = <29>;
|
||||
reg-shift = <0>;
|
||||
fifo-size = <16>;
|
||||
reg-io-width = <1>;
|
||||
current-speed = <115200>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
resets = <&reset 22>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
};
|
||||
127
Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt
Normal file
127
Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt
Normal file
|
|
@ -0,0 +1,127 @@
|
|||
Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.
|
||||
|
||||
Device has 8 GPIO pins which can be configured as GPIO as well as the
|
||||
special IO functions.
|
||||
|
||||
Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
|
||||
for details of the common pinctrl bindings used by client devices,
|
||||
including the meaning of the phrase "pin configuration node".
|
||||
|
||||
Optional Pinmux properties:
|
||||
--------------------------
|
||||
Following properties are required if default setting of pins are required
|
||||
at boot.
|
||||
- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
|
||||
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
|
||||
<pinctrl-binding.txt>.
|
||||
|
||||
The pin configurations are defined as child of the pinctrl states node. Each
|
||||
sub-node have following properties:
|
||||
|
||||
Required properties:
|
||||
------------------
|
||||
- pins: List of pins. Valid values of pins properties are:
|
||||
gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7.
|
||||
|
||||
Optional properties:
|
||||
-------------------
|
||||
Following are optional properties defined as pinmux DT binding document
|
||||
<pinctrl-bindings.txt>. Absence of properties will leave the configuration
|
||||
on default.
|
||||
function,
|
||||
drive-push-pull,
|
||||
drive-open-drain,
|
||||
bias-pull-up,
|
||||
bias-pull-down.
|
||||
|
||||
Valid values for function properties are:
|
||||
gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in,
|
||||
reference-out
|
||||
|
||||
Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These
|
||||
customised properties are required to configure FPS configuration parameters
|
||||
of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more
|
||||
detail of Flexible Power Sequence (FPS).
|
||||
|
||||
- maxim,active-fps-source: FPS source for the GPIOs to get
|
||||
enabled/disabled when system is in
|
||||
active state. Valid values are:
|
||||
- MAX77620_FPS_SRC_0,
|
||||
FPS source is FPS0.
|
||||
- MAX77620_FPS_SRC_1,
|
||||
FPS source is FPS1
|
||||
- MAX77620_FPS_SRC_2 and
|
||||
FPS source is FPS2
|
||||
- MAX77620_FPS_SRC_NONE.
|
||||
GPIO is not controlled
|
||||
by FPS events and it gets
|
||||
enabled/disabled by register
|
||||
access.
|
||||
Absence of this property will leave
|
||||
the FPS configuration register for that
|
||||
GPIO to default configuration.
|
||||
|
||||
- maxim,active-fps-power-up-slot: Sequencing event slot number on which
|
||||
the GPIO get enabled when
|
||||
master FPS input event set to HIGH.
|
||||
Valid values are 0 to 7.
|
||||
This is applicable if FPS source is
|
||||
selected as FPS0, FPS1 or FPS2.
|
||||
|
||||
- maxim,active-fps-power-down-slot: Sequencing event slot number on which
|
||||
the GPIO get disabled when master
|
||||
FPS input event set to LOW.
|
||||
Valid values are 0 to 7.
|
||||
This is applicable if FPS source is
|
||||
selected as FPS0, FPS1 or FPS2.
|
||||
|
||||
- maxim,suspend-fps-source: This is same as property
|
||||
"maxim,active-fps-source" but value
|
||||
get configured when system enters in
|
||||
to suspend state.
|
||||
|
||||
- maxim,suspend-fps-power-up-slot: This is same as property
|
||||
"maxim,active-fps-power-up-slot" but
|
||||
this value get configured into FPS
|
||||
configuration register when system
|
||||
enters into suspend.
|
||||
This is applicable if suspend state
|
||||
FPS source is selected as FPS0, FPS1 or
|
||||
|
||||
- maxim,suspend-fps-power-down-slot: This is same as property
|
||||
"maxim,active-fps-power-down-slot" but
|
||||
this value get configured into FPS
|
||||
configuration register when system
|
||||
enters into suspend.
|
||||
This is applicable if suspend state
|
||||
FPS source is selected as FPS0, FPS1 or
|
||||
FPS2.
|
||||
|
||||
Example:
|
||||
--------
|
||||
#include <dt-bindings/mfd/max77620.h>
|
||||
...
|
||||
max77620@3c {
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spmic_default>;
|
||||
|
||||
spmic_default: pinmux@0 {
|
||||
pin_gpio0 {
|
||||
pins = "gpio0";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
pin_gpio1 {
|
||||
pins = "gpio1";
|
||||
function = "fps-out";
|
||||
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
|
||||
};
|
||||
|
||||
pin_gpio2 {
|
||||
pins = "gpio2";
|
||||
function = "fps-out";
|
||||
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
Qualcomm MDM9615 TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
MDM9615 platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,mdm9615-pinctrl"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the TLMM register space.
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode. Valid pins are:
|
||||
gpio0-gpio87
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins.
|
||||
Valid values are:
|
||||
gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
|
||||
sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio,
|
||||
cdc_mclk
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configued as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configued as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configued as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
msmgpio: pinctrl@800000 {
|
||||
compatible = "qcom,mdm9615-pinctrl";
|
||||
reg = <0x800000 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 16 0x4>;
|
||||
|
||||
gsbi8_uart: gsbi8-uart {
|
||||
mux {
|
||||
pins = "gpio34", "gpio35";
|
||||
function = "gsbi8";
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio34";
|
||||
drive-strength = <4>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rx {
|
||||
pins = "gpio35";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -52,7 +52,7 @@ Valid values for function are:
|
|||
gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n,
|
||||
gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s,
|
||||
lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1,
|
||||
usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm,
|
||||
usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
|||
|
|
@ -49,6 +49,9 @@ Valid values for pins are:
|
|||
sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data
|
||||
Supports bias and drive-strength
|
||||
|
||||
hsic_data, hsic_strobe
|
||||
Supports only mux
|
||||
|
||||
Valid values for function are:
|
||||
cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
|
||||
blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1,
|
||||
|
|
@ -70,7 +73,7 @@ Valid values for function are:
|
|||
cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc,
|
||||
hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk,
|
||||
gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s,
|
||||
ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, gpio
|
||||
ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl, gpio
|
||||
|
||||
(Note that this is not yet the complete list of functions)
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ of PMIC's from Qualcomm.
|
|||
Definition: Should contain one of:
|
||||
"qcom,pm8018-mpp",
|
||||
"qcom,pm8038-mpp",
|
||||
"qcom,pm8058-mpp",
|
||||
"qcom,pm8821-mpp",
|
||||
"qcom,pm8841-mpp",
|
||||
"qcom,pm8916-mpp",
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ Pin Configuration Node Properties:
|
|||
|
||||
The pin configuration parameters use the generic pinconf bindings defined in
|
||||
pinctrl-bindings.txt in this directory. The supported parameters are
|
||||
bias-disable, bias-pull-up, bias-pull-down, drive strength and power-source. For
|
||||
bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For
|
||||
pins that have a configurable I/O voltage, the power-source value should be the
|
||||
nominal I/O voltage in millivolts.
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ Pin controller node:
|
|||
Required properies:
|
||||
- compatible: value should be one of the following:
|
||||
(a) "st,stm32f429-pinctrl"
|
||||
(b) "st,stm32f746-pinctrl"
|
||||
- #address-cells: The value of this property must be 1
|
||||
- #size-cells : The value of this property must be 1
|
||||
- ranges : defines mapping between pin controller node (parent) to
|
||||
|
|
|
|||
Loading…
Reference in a new issue