From da2773ed0fc2327e3dd33a42a3c4d8b9364aabff Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 24 Apr 2020 20:10:00 +0530 Subject: [PATCH] clk: qcom: gcc-shima: Add support for ref clocks Add support for gcc_gpu_iref_en and gcc_ufs_1_clkref_en in GCC for SHIMA. Change-Id: I826cbbc8869816584c6113fd2c873b59085ec998 Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/gcc-shima.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/clk/qcom/gcc-shima.c b/drivers/clk/qcom/gcc-shima.c index 4b85be3c521e..467bf324d560 100644 --- a/drivers/clk/qcom/gcc-shima.c +++ b/drivers/clk/qcom/gcc-shima.c @@ -1832,6 +1832,19 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { }, }; +static struct clk_branch gcc_gpu_iref_en = { + .halt_reg = 0x8c014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_iref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_gpu_memnoc_gfx_clk = { .halt_reg = 0x7100c, .halt_check = BRANCH_HALT_VOTED, @@ -2796,6 +2809,19 @@ static struct clk_branch gcc_titan_rt_throttle_core_clk = { }, }; +static struct clk_branch gcc_ufs_1_clkref_en = { + .halt_reg = 0x8c000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_1_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_phy_ahb_clk = { .halt_reg = 0x77018, .halt_check = BRANCH_HALT_VOTED, @@ -3257,6 +3283,7 @@ static struct clk_regmap *gcc_shima_clocks[] = { [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr, @@ -3345,6 +3372,7 @@ static struct clk_regmap *gcc_shima_clocks[] = { [GCC_TITAN_NRT_THROTTLE_CORE_CLK] = &gcc_titan_nrt_throttle_core_clk.clkr, [GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr, + [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr, [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,