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ARM: dts: msm: correct dcc offset on sdxlemur
The first 2KB should be reserved for TZ, so correct the offset to 0x800. Change-Id: I1f4b0ad01865e3374252a54074c5bd1f5fa02b7e
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1 changed files with 2 additions and 2 deletions
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@ -221,12 +221,12 @@
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dcc: dcc_v2@117f000 {
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compatible = "qcom,dcc-v2";
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reg = <0x117f000 0x1000>,
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<0x1100000 0x2000>;
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<0x1100800 0x1800>;
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qcom,transaction_timeout = <0>;
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reg-names = "dcc-base", "dcc-ram-base";
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dcc-ram-offset = <0x12000>;
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dcc-ram-offset = <0x800>;
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link_list1 {
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qcom,curr-link-list = <2>;
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