ARM: dts: msm: correct dcc offset on sdxlemur

The first 2KB should be reserved for TZ, so correct the offset to
0x800.

Change-Id: I1f4b0ad01865e3374252a54074c5bd1f5fa02b7e
This commit is contained in:
Yuanfang Zhang 2021-03-03 19:04:24 +08:00
commit daa016e980

View file

@ -221,12 +221,12 @@
dcc: dcc_v2@117f000 {
compatible = "qcom,dcc-v2";
reg = <0x117f000 0x1000>,
<0x1100000 0x2000>;
<0x1100800 0x1800>;
qcom,transaction_timeout = <0>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x12000>;
dcc-ram-offset = <0x800>;
link_list1 {
qcom,curr-link-list = <2>;