diff --git a/drivers/gpu/msm/adreno_iommu.c b/drivers/gpu/msm/adreno_iommu.c
index e3bafea479de..07defc3c81b7 100644
--- a/drivers/gpu/msm/adreno_iommu.c
+++ b/drivers/gpu/msm/adreno_iommu.c
@@ -188,6 +188,8 @@ static unsigned int _adreno_iommu_set_pt_v2_a5xx(struct kgsl_device *device,
 	*cmds++ = contextidr;
 
 
+	*cmds++ = cp_type7_packet(CP_WAIT_FOR_IDLE, 0);
+	*cmds++ = cp_type7_packet(CP_WAIT_FOR_ME, 0);
 	*cmds++ = cp_type4_packet(A5XX_CP_CNTL, 1);
 	*cmds++ = 1;
 
@@ -198,6 +200,8 @@ static unsigned int _adreno_iommu_set_pt_v2_a5xx(struct kgsl_device *device,
 	*cmds++ = upper_32_bits(ttbr0);
 	*cmds++ = contextidr;
 
+	*cmds++ = cp_type7_packet(CP_WAIT_FOR_IDLE, 0);
+	*cmds++ = cp_type7_packet(CP_WAIT_FOR_ME, 0);
 	*cmds++ = cp_type4_packet(A5XX_CP_CNTL, 1);
 	*cmds++ = 0;
 
@@ -221,6 +225,8 @@ static unsigned int _adreno_iommu_set_pt_v2_a6xx(struct kgsl_device *device,
 	*cmds++ = cb_num;
 
 	if (!ADRENO_FEATURE(adreno_dev, ADRENO_APRIV)) {
+		*cmds++ = cp_type7_packet(CP_WAIT_FOR_IDLE, 0);
+		*cmds++ = cp_type7_packet(CP_WAIT_FOR_CP_FLUSH, 0);
 		*cmds++ = cp_type4_packet(A6XX_CP_MISC_CNTL, 1);
 		*cmds++ = 1;
 	}
@@ -233,6 +239,8 @@ static unsigned int _adreno_iommu_set_pt_v2_a6xx(struct kgsl_device *device,
 	*cmds++ = contextidr;
 
 	if (!ADRENO_FEATURE(adreno_dev, ADRENO_APRIV)) {
+		*cmds++ = cp_type7_packet(CP_WAIT_FOR_IDLE, 0);
+		*cmds++ = cp_type7_packet(CP_WAIT_FOR_CP_FLUSH, 0);
 		*cmds++ = cp_type4_packet(A6XX_CP_MISC_CNTL, 1);
 		*cmds++ = 0;
 	}
diff --git a/drivers/gpu/msm/adreno_pm4types.h b/drivers/gpu/msm/adreno_pm4types.h
index 8be6637b088a..b64492044400 100644
--- a/drivers/gpu/msm/adreno_pm4types.h
+++ b/drivers/gpu/msm/adreno_pm4types.h
@@ -122,6 +122,9 @@
 /* PFP waits until the FIFO between the PFP and the ME is empty */
 #define CP_WAIT_FOR_ME		0x13
 
+/* Stall the SQE until the CP processing pipeline is empty */
+#define CP_WAIT_FOR_CP_FLUSH 0x13
+
 #define CP_SET_PROTECTED_MODE  0x5f /* sets the register protection mode */
 
 /* Used to switch GPU between secure and non-secure modes */