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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 08:36:12 -04:00
ARM: dts: msm: Enable PCIe RC on sdxnightjar
Add devicetree node to enable PCIe Root Complex on sdxnightjar. Change-Id: I95d155d9ffa9a4fe8c690b18fa8e4beaf94695f9
This commit is contained in:
Siva Kumar Akkireddi
parent
182b5ec035
commit
daec517500
2 changed files with 160 additions and 0 deletions
159
qcom/sdxnightjar-pcie.dtsi
Normal file
159
qcom/sdxnightjar-pcie.dtsi
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@ -0,0 +1,159 @@
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&soc {
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pcie0: qcom,pcie@80000 {
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compatible = "qcom,pci-msm";
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reg = <0x80000 0x2000>,
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<0x86000 0x1000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40100000 0x100000>,
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<0x01956044 0x4>;
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reg-names = "parf", "phy", "dm_core", "elbi", "conf", "tcsr";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm_pinmux 60 0>;
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wake-gpio = <&tlmm_pinmux 61 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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gdsc-vdd-supply = <&gdsc_pcie>;
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vreg-1p8-supply = <&pmd9650_l5>;
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vreg-0p9-supply = <&pmd9650_l4>;
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qcom,vreg-0.9-voltage-level = <928000 928000 24000>;
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interconnect-names = "icc_path";
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interconnects = <&system_noc MASTER_PCIE &bimc SLAVE_EBI_CH0>;
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clocks = <&gcc GCC_PCIE_PIPE_CLK>,
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<&rpmcc RPM_SMD_LN_BB_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_AXI_MSTR_CLK>,
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<&gcc GCC_PCIE_AXI_CLK>,
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<&gcc GCC_PCIE_REF_CLK>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo";
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max-clock-frequency-hz = <0>, <0>, <19200000>,
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<0>, <0>, <0>, <0>, <0>;
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resets = <&gcc GCC_PCIE_PHY_BCR>,
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<&gcc GCC_PCIEPHY_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_phy_reset";
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qcom,aux-clk-freq = <0x14>;
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qcom,ep-latency = <10>;
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qcom,boot-option = <0x1>;
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qcom,pcie-phy-ver = <0x10>;
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qcom,phy-status-offset = <0x974>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x804>;
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qcom,phy-sequence = <0x800 0x01 0x0
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0x804 0x03 0x0
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0x034 0x18 0x0
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0x038 0x10 0x0
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0x294 0x06 0x0
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0x0c8 0x01 0x0
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0x128 0x00 0x0
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0x144 0xff 0x0
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0x148 0x1f 0x0
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0x070 0x0f 0x0
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0x048 0x0f 0x0
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0x178 0x00 0x0
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0x19c 0x01 0x0
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0x18c 0x20 0x0
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0x184 0x0a 0x0
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0x00c 0x09 0x0
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0x0ac 0x04 0x0
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0x0d0 0x82 0x0
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0x0e4 0x03 0x0
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0x0e0 0x55 0x0
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0x0dc 0x55 0x0
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0x054 0x00 0x0
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0x050 0x0d 0x0
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0x04c 0x04 0x0
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0x174 0x33 0x0
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0x03c 0x02 0x0
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0x040 0x1f 0x0
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0x078 0x0b 0x0
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0x084 0x16 0x0
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0x090 0x28 0x0
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0x10c 0x00 0x0
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0x108 0x80 0x0
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0x010 0x01 0x0
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0x01c 0x31 0x0
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0x020 0x01 0x0
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0x014 0x02 0x0
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0x018 0x00 0x0
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0x024 0x2f 0x0
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0x028 0x19 0x0
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0x268 0x45 0x0
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0x194 0x06 0x0
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0x254 0x02 0x0
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0x2ac 0x12 0x0
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0x510 0x1c 0x0
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0x51c 0x14 0x0
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0x4d8 0x01 0x0
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0x4dc 0x00 0x0
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0x4e0 0xdb 0x0
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0x448 0x4b 0x0
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0x41c 0x04 0x0
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0x410 0x04 0x0
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0x074 0x19 0x0
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0x854 0x04 0x0
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0x9ac 0x00 0x0
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0x8a0 0x40 0x0
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0x9e0 0x00 0x0
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0x9dc 0x40 0x0
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0x9a8 0x00 0x0
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0x8a4 0x40 0x0
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0x8a8 0x73 0x0
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0x518 0x99 0x0
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0x824 0x15 0x0
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0x828 0x0e 0x0
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0x9b0 0x07 0x0
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0x800 0x00 0x0
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0x808 0x03 0x0>;
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@a0000000 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0xa0000000 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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qcom,snps;
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};
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};
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@ -984,6 +984,7 @@
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#include "sdxnightjar-coresight.dtsi"
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#include "sdxnightjar-pinctrl.dtsi"
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#include "sdxnightjar-blsp.dtsi"
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#include "sdxnightjar-pcie.dtsi"
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&i2c_3 {
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status = "ok"
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