From db2bf3235834196b9d5776ce949ef126cfb1e8f4 Mon Sep 17 00:00:00 2001
From: Alok Pandey <akumarpa@qti.qualcomm.com>
Date: Wed, 27 Jan 2021 22:31:37 +0530
Subject: [PATCH] ARM: dts: msm: fix for Shima-CAMNOC RDI latency buffer
 corruption

This is a fix to handle line corruption on RDI stream by capping
IPE clock to SVS. It will help to avoid back pressure on CAMNOC
dur to IPE traffic. This gives more room to IFE RDI stream and hence
avoid corruption.

CRs-Fixed: 2887253
Change-Id: I8880c08d507ebb90b447815a241870d03fd24bec
---
 shima-camera.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/shima-camera.dtsi b/shima-camera.dtsi
index b8d06d5f711e..7571aa22b285 100644
--- a/shima-camera.dtsi
+++ b/shima-camera.dtsi
@@ -1215,9 +1215,9 @@
 		clock-rates =
 			<0 0 0 300000000 0>,
 			<0 0 0 450000000 0>,
-			<0 0 0 525000000 0>,
-			<0 0 0 700000000 0>,
-			<0 0 0 700000000 0>;
+			<0 0 0 450000000 0>,
+			<0 0 0 450000000 0>,
+			<0 0 0 450000000 0>;
 		clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
 			"turbo";
 		status = "ok";