From db3567cce04a3a1b88f05d98b7b9d73fccd3749e Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Mon, 19 Jun 2023 13:57:06 +0800 Subject: [PATCH] charge:optimize the cp enable in ESR Sometimes the cell voltage exceed the max limit when pump disable/enable. Only allow the pump enable/disable when soc is lower than 90%. Change-Id: I775d22ee7491cd25e2a3a53fbbb5472c80cc8fc6 Signed-off-by: Lei Chen Reviewed-on: https://gerrit.mot.com/2647497 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver Tested-by: Jira Key Reviewed-by: Xiangpo Zhao Reviewed-by: Wei Xu Submit-Approved: Jira Key --- drivers/power/supply/qcom/qg-core.h | 1 + drivers/power/supply/qcom/qpnp-qg.c | 15 +++++++++++---- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/power/supply/qcom/qg-core.h b/drivers/power/supply/qcom/qg-core.h index 5c099d1d8168..9ee46f79ed4a 100644 --- a/drivers/power/supply/qcom/qg-core.h +++ b/drivers/power/supply/qcom/qg-core.h @@ -66,6 +66,7 @@ struct qg_dt { int fvss_vbat_mv; int tcss_entry_soc; int esr_low_temp_threshold; + int cp_chrg_soc_limit; bool hold_soc_while_full; bool linearize_soc; bool cl_disable; diff --git a/drivers/power/supply/qcom/qpnp-qg.c b/drivers/power/supply/qcom/qpnp-qg.c index 4150966bd5f6..7351d60a3563 100644 --- a/drivers/power/supply/qcom/qpnp-qg.c +++ b/drivers/power/supply/qcom/qpnp-qg.c @@ -1103,12 +1103,12 @@ static int qg_esr_estimate(struct qpnp_qg *chip) goto done; } - if (chip->dt.cp_use_internal_qg) { + if ((chip->dt.cp_use_internal_qg) && (chip->msoc < chip->dt.cp_chrg_soc_limit)) { rc = qg_write_iio_chan(chip, CP_CHARGING_ENABLED, 0); if (rc < 0) pr_err("Failed to force disable cp rc=%d\n", rc); else - qg_dbg(chip, QG_DEBUG_STATUS, "disable cp\n"); + qg_dbg(chip, QG_DEBUG_STATUS, "disable cp, msoc =%d\n",chip->msoc); msleep(1000); } @@ -1200,12 +1200,12 @@ static int qg_esr_estimate(struct qpnp_qg *chip) msleep(200); } - if (chip->dt.cp_use_internal_qg) { + if ((chip->dt.cp_use_internal_qg) && (chip->msoc < chip->dt.cp_chrg_soc_limit)) { rc = qg_write_iio_chan(chip, CP_CHARGING_ENABLED, 1); if (rc < 0) pr_err("Failed to force enable cp rc=%d\n", rc); else - qg_dbg(chip, QG_DEBUG_STATUS, "enable cp\n"); + qg_dbg(chip, QG_DEBUG_STATUS, "enable cp, msoc =%d\n",chip->msoc); } rc = qg_process_esr_data(chip); @@ -4392,6 +4392,13 @@ static int qg_parse_dt(struct qpnp_qg *chip) "qcom,esr-discharge-enable"); chip->dt.cp_use_internal_qg = of_property_read_bool(node, "mmi,cp-use-internal-qg"); + + rc = of_property_read_u32(node, "mmi,cp-chrg-soc-limit", &temp); + if (rc < 0) + chip->dt.cp_chrg_soc_limit = 100; + else + chip->dt.cp_chrg_soc_limit = temp; + rc = of_property_read_u32(node, "qcom,esr-qual-current-ua", &temp); if (rc < 0) chip->dt.esr_qual_i_ua = DEFAULT_ESR_QUAL_CURRENT_UA;