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ARM: dts: msm: Enable NAND and SD card for sdxnightjar

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Enable NAND and SD card for sdxnightjar.

Change-Id: I7381fc7bbfa2c086bdd62593e28362d9e0a97bef
This commit is contained in:
Sarthak Garg 2020-11-22 20:02:25 +05:30
commit db4a7ceebb
5 changed files with 165 additions and 0 deletions
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19
qcom/sdxnightjar-cdp.dtsi
View file

@ -4,3 +4,22 @@
pinctrl-0 = <&uart3_console_active>;
};
&qnand_1 {
status = "ok"
};
&sdhc_1 {
vdd-supply = <&sdc_vreg>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&pmd9650_l7>;
qcom,vdd-io-voltage-level = <1800000 2848000>;
qcom,vdd-io-current-level = <0 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
status = "ok"
};

19
qcom/sdxnightjar-mtp.dtsi
View file

@ -4,3 +4,22 @@
pinctrl-0 = <&uart3_console_active>;
};
&qnand_1 {
status = "ok"
};
&sdhc_1 {
vdd-supply = <&sdc_vreg>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&pmd9650_l7>;
qcom,vdd-io-voltage-level = <1800000 2848000>;
qcom,vdd-io-current-level = <0 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
status = "ok"
};

40
qcom/sdxnightjar-pinctrl.dtsi
View file

@ -401,6 +401,46 @@
};
};
sdc2_on: sdc2_on {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
};
sdc2_off: sdc2_off {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
};
/* SMB CONFIGURATION */
pmx_smb_stat {
smb_stat_active: smb_stat_active {

19
qcom/sdxnightjar-qrd.dtsi
View file

@ -4,3 +4,22 @@
pinctrl-0 = <&uart3_console_active>;
};
&qnand_1 {
status = "ok"
};
&sdhc_1 {
vdd-supply = <&sdc_vreg>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&pmd9650_l7>;
qcom,vdd-io-voltage-level = <1800000 2848000>;
qcom,vdd-io-current-level = <0 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
status = "ok"
};

68
qcom/sdxnightjar.dtsi
View file

@ -542,6 +542,74 @@
};
};
qnand_1: nand@7980000 {
compatible = "qcom,msm-nand";
reg = <0x07980000 0x1000>,
<0x07984000 0x1a000>;
reg-names = "nand_phys",
"bam_phys";
qcom,reg-adjustment-offset = <0x4000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bam_irq";
clock-names = "core_clk";
clocks = <&rpmcc RPM_SMD_QPIC_CLK>;
interconnects = <&pc_noc MASTER_QPIC &bimc SLAVE_EBI_CH0>;
interconnect-names = "nand-ddr";
qcom,msm-bus,name = "qpic_nand";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<0 0>,
/* Voting for max b/w on PNOC bus for now */
<400000 400000>;
status = "disabled";
};
sdhc_1: sdhci@7824000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x07824900 0x500>, <0x07824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,devfreq,freq-table = <50000000 200000000>;
interconnects = <&pc_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>;
interconnect-names = "sdhc-ddr";
qcom,msm-bus,name = "sdhc1";
qcom,msm-bus,num-cases = <7>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <0 0>, /* No vote */
<1600 3200>, /* 400 KB/s*/
<100000 200000>, /* 25 MB/s */
<200000 400000>, /* 50 MB/s */
<400000 800000>, /* 100 MB/s */
<400000 800000>, /* 200 MB/s */
<2048000 4096000>; /* Max. bandwidth */
qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
100000000 200000000 4294967295>;
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>;
clock-names = "iface", "core";
bus-width = <4>;
status = "disabled";
qos0 {
mask = <0x1>;
vote = <70>;
};
};
spmi_bus: qcom,spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f000 0x1000>,