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msm: kgsl: Program GPU SCID for UCHE traffic

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The UCHE traffic for graphics(i.e. non LPAC) usecases is a
different MID on a660 and it's GPU SCID programming is done in
A6XX_GBIF_SCACHE_CNTL0.

Change-Id: I2ce73ef8b4f171b106eb59c6d998e201c6d2ec75
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This commit is contained in:
Harshdeep Dhatt 2020-03-03 16:05:32 -07:00
commit dba879bd16
2 changed files with 9 additions and 0 deletions
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1
drivers/gpu/msm/a6xx_reg.h
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@ -826,6 +826,7 @@
#define GBIF_AXI1_WRITE_DATA_TOTAL_BEATS 47
/* GBIF registers */
#define A6XX_GBIF_SCACHE_CNTL0 0x3c01
#define A6XX_GBIF_SCACHE_CNTL1 0x3c02
#define A6XX_GBIF_QSB_SIDE0 0x3c03
#define A6XX_GBIF_QSB_SIDE1 0x3c04

8
drivers/gpu/msm/adreno_a6xx.c
View file

@ -1219,6 +1219,14 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev)
adreno_cx_misc_regrmw(adreno_dev,
A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,
A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);
/*
* On A660, the SCID programming for UCHE traffic is done in
* A6XX_GBIF_SCACHE_CNTL0[14:10]
*/
if (adreno_is_a660(adreno_dev))
kgsl_regrmw(device, A6XX_GBIF_SCACHE_CNTL0, 0x1f << 10,
gpu_scid << 10);
}
/*