mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 07:37:31 -04:00
Merge "clk: qcom: debugcc-yupik: Update all PCIE clocks to measure only"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
dbb084194a
1 changed files with 220 additions and 40 deletions
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@ -281,9 +281,6 @@ static const char *const gcc_debug_mux_parent_names[] = {
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"apss_cc_debug_mux",
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"cam_cc_debug_mux",
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"disp_cc_debug_mux",
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"gcc_aggre_noc_pcie_0_axi_clk",
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"gcc_aggre_noc_pcie_1_axi_clk",
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"gcc_aggre_noc_pcie_center_sf_axi_clk",
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"gcc_aggre_ufs_phy_axi_clk",
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"gcc_aggre_usb3_prim_axi_clk",
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"gcc_aggre_usb3_sec_axi_clk",
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@ -292,7 +289,6 @@ static const char *const gcc_debug_mux_parent_names[] = {
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"gcc_cfg_noc_usb3_prim_axi_clk",
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"gcc_cfg_noc_usb3_sec_axi_clk",
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"gcc_ddrss_gpu_axi_clk",
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"gcc_ddrss_pcie_sf_clk",
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"gcc_disp_gpll0_clk_src",
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"gcc_disp_hf_axi_clk",
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"gcc_disp_sf_axi_clk",
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@ -303,21 +299,6 @@ static const char *const gcc_debug_mux_parent_names[] = {
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"gcc_gpu_gpll0_div_clk_src",
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"gcc_gpu_memnoc_gfx_clk",
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"gcc_gpu_snoc_dvm_gfx_clk",
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"gcc_pcie0_phy_rchng_clk",
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"gcc_pcie1_phy_rchng_clk",
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"gcc_pcie_0_aux_clk",
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"gcc_pcie_0_cfg_ahb_clk",
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"gcc_pcie_0_mstr_axi_clk",
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"gcc_pcie_0_pipe_clk",
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"gcc_pcie_0_slv_axi_clk",
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"gcc_pcie_0_slv_q2a_axi_clk",
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"gcc_pcie_1_aux_clk",
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"gcc_pcie_1_cfg_ahb_clk",
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"gcc_pcie_1_mstr_axi_clk",
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"gcc_pcie_1_pipe_clk",
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"gcc_pcie_1_slv_axi_clk",
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"gcc_pcie_1_slv_q2a_axi_clk",
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"gcc_pcie_throttle_core_clk",
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"gcc_pdm2_clk",
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"gcc_pdm_ahb_clk",
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"gcc_pdm_xo4_clk",
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@ -356,7 +337,6 @@ static const char *const gcc_debug_mux_parent_names[] = {
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"gcc_sdcc2_apps_clk",
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"gcc_sdcc4_ahb_clk",
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"gcc_sdcc4_apps_clk",
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"gcc_throttle_pcie_ahb_clk",
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"gcc_titan_nrt_throttle_core_clk",
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"gcc_titan_rt_throttle_core_clk",
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"gcc_ufs_phy_ahb_clk",
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@ -384,11 +364,31 @@ static const char *const gcc_debug_mux_parent_names[] = {
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"gpu_cc_debug_mux",
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"mc_cc_debug_mux",
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"measure_only_cnoc_clk",
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"measure_only_gcc_aggre_noc_pcie_0_axi_clk",
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"measure_only_gcc_aggre_noc_pcie_1_axi_clk",
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"measure_only_gcc_aggre_noc_pcie_center_sf_axi_clk",
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"measure_only_gcc_camera_ahb_clk",
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"measure_only_gcc_camera_xo_clk",
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"measure_only_gcc_ddrss_pcie_sf_clk",
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"measure_only_gcc_disp_ahb_clk",
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"measure_only_gcc_disp_xo_clk",
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"measure_only_gcc_gpu_cfg_ahb_clk",
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"measure_only_gcc_pcie0_phy_rchng_clk",
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"measure_only_gcc_pcie1_phy_rchng_clk",
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"measure_only_gcc_pcie_0_aux_clk",
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"measure_only_gcc_pcie_0_cfg_ahb_clk",
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"measure_only_gcc_pcie_0_mstr_axi_clk",
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"measure_only_gcc_pcie_0_pipe_clk",
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"measure_only_gcc_pcie_0_slv_axi_clk",
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"measure_only_gcc_pcie_0_slv_q2a_axi_clk",
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"measure_only_gcc_pcie_1_aux_clk",
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"measure_only_gcc_pcie_1_cfg_ahb_clk",
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"measure_only_gcc_pcie_1_mstr_axi_clk",
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"measure_only_gcc_pcie_1_pipe_clk",
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"measure_only_gcc_pcie_1_slv_axi_clk",
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"measure_only_gcc_pcie_1_slv_q2a_axi_clk",
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"measure_only_gcc_pcie_throttle_core_clk",
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"measure_only_gcc_throttle_pcie_ahb_clk",
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"measure_only_gcc_video_ahb_clk",
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"measure_only_gcc_video_xo_clk",
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"measure_only_ipa_2x_clk",
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@ -407,9 +407,6 @@ static int gcc_debug_mux_sels[] = {
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0xED, /* apss_cc_debug_mux */
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0x4E, /* cam_cc_debug_mux */
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0x54, /* disp_cc_debug_mux */
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0x12C, /* gcc_aggre_noc_pcie_0_axi_clk */
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0x12D, /* gcc_aggre_noc_pcie_1_axi_clk */
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0x172, /* gcc_aggre_noc_pcie_center_sf_axi_clk */
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0x12F, /* gcc_aggre_ufs_phy_axi_clk */
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0x12E, /* gcc_aggre_usb3_prim_axi_clk */
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0x170, /* gcc_aggre_usb3_sec_axi_clk */
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@ -418,7 +415,6 @@ static int gcc_debug_mux_sels[] = {
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0x1B, /* gcc_cfg_noc_usb3_prim_axi_clk */
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0x1C, /* gcc_cfg_noc_usb3_sec_axi_clk */
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0xCD, /* gcc_ddrss_gpu_axi_clk */
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0xCE, /* gcc_ddrss_pcie_sf_clk */
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0x45, /* gcc_disp_gpll0_clk_src */
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0x51, /* gcc_disp_hf_axi_clk */
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0x52, /* gcc_disp_sf_axi_clk */
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@ -429,21 +425,6 @@ static int gcc_debug_mux_sels[] = {
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0x14C, /* gcc_gpu_gpll0_div_clk_src */
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0x147, /* gcc_gpu_memnoc_gfx_clk */
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0x14A, /* gcc_gpu_snoc_dvm_gfx_clk */
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0x101, /* gcc_pcie0_phy_rchng_clk */
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0x10A, /* gcc_pcie1_phy_rchng_clk */
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0xFF, /* gcc_pcie_0_aux_clk */
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0xFE, /* gcc_pcie_0_cfg_ahb_clk */
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0xFD, /* gcc_pcie_0_mstr_axi_clk */
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0x100, /* gcc_pcie_0_pipe_clk */
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0xFC, /* gcc_pcie_0_slv_axi_clk */
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0xFB, /* gcc_pcie_0_slv_q2a_axi_clk */
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0x108, /* gcc_pcie_1_aux_clk */
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0x107, /* gcc_pcie_1_cfg_ahb_clk */
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0x106, /* gcc_pcie_1_mstr_axi_clk */
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0x109, /* gcc_pcie_1_pipe_clk */
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0x105, /* gcc_pcie_1_slv_axi_clk */
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0x104, /* gcc_pcie_1_slv_q2a_axi_clk */
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0x30, /* gcc_pcie_throttle_core_clk */
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0xA4, /* gcc_pdm2_clk */
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0xA2, /* gcc_pdm_ahb_clk */
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0xA3, /* gcc_pdm_xo4_clk */
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@ -482,7 +463,6 @@ static int gcc_debug_mux_sels[] = {
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0x86, /* gcc_sdcc2_apps_clk */
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0x89, /* gcc_sdcc4_ahb_clk */
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0x88, /* gcc_sdcc4_apps_clk */
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0x3A, /* gcc_throttle_pcie_ahb_clk */
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0x4C, /* gcc_titan_nrt_throttle_core_clk */
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0x4A, /* gcc_titan_rt_throttle_core_clk */
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0x10E, /* gcc_ufs_phy_ahb_clk */
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@ -510,11 +490,31 @@ static int gcc_debug_mux_sels[] = {
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0x146, /* gpu_cc_debug_mux */
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0xD7, /* mc_cc_debug_mux or ddrss_gcc_debug_clk */
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0x17, /* measure_only_cnoc_clk */
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0x12C, /* measure_only_gcc_aggre_noc_pcie_0_axi_clk */
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0x12D, /* measure_only_gcc_aggre_noc_pcie_1_axi_clk */
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0x172, /* measure_only_gcc_aggre_noc_pcie_center_sf_axi_clk */
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0x46, /* measure_only_gcc_camera_ahb_clk */
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0x4D, /* measure_only_gcc_camera_xo_clk */
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0xCE, /* measure_only_gcc_ddrss_pcie_sf_clk */
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0x4F, /* measure_only_gcc_disp_ahb_clk */
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0x53, /* measure_only_gcc_disp_xo_clk */
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0x144, /* measure_only_gcc_gpu_cfg_ahb_clk */
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0x101, /* measure_only_gcc_pcie0_phy_rchng_clk */
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0x10A, /* measure_only_gcc_pcie1_phy_rchng_clk */
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0xFF, /* measure_only_gcc_pcie_0_aux_clk */
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0xFE, /* measure_only_gcc_pcie_0_cfg_ahb_clk */
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0xFD, /* measure_only_gcc_pcie_0_mstr_axi_clk */
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0x100, /* measure_only_gcc_pcie_0_pipe_clk */
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0xFC, /* measure_only_gcc_pcie_0_slv_axi_clk */
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0xFB, /* measure_only_gcc_pcie_0_slv_q2a_axi_clk */
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0x108, /* measure_only_gcc_pcie_1_aux_clk */
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0x107, /* measure_only_gcc_pcie_1_cfg_ahb_clk */
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0x106, /* measure_only_gcc_pcie_1_mstr_axi_clk */
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0x109, /* measure_only_gcc_pcie_1_pipe_clk */
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0x105, /* measure_only_gcc_pcie_1_slv_axi_clk */
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0x104, /* measure_only_gcc_pcie_1_slv_q2a_axi_clk */
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0x30, /* measure_only_gcc_pcie_throttle_core_clk */
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0x3A, /* measure_only_gcc_throttle_pcie_ahb_clk */
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0x55, /* measure_only_gcc_video_ahb_clk */
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0x5C, /* measure_only_gcc_video_xo_clk */
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0x132, /* measure_only_ipa_2x_clk */
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@ -722,6 +722,30 @@ static struct clk_dummy measure_only_disp_cc_xo_clk = {
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},
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};
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static struct clk_dummy measure_only_gcc_aggre_noc_pcie_0_axi_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_aggre_noc_pcie_0_axi_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_aggre_noc_pcie_1_axi_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_aggre_noc_pcie_1_axi_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_aggre_noc_pcie_center_sf_axi_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_aggre_noc_pcie_center_sf_axi_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_camera_ahb_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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@ -738,6 +762,14 @@ static struct clk_dummy measure_only_gcc_camera_xo_clk = {
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},
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};
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static struct clk_dummy measure_only_gcc_ddrss_pcie_sf_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_ddrss_pcie_sf_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_disp_ahb_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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@ -762,6 +794,134 @@ static struct clk_dummy measure_only_gcc_gpu_cfg_ahb_clk = {
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},
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};
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static struct clk_dummy measure_only_gcc_pcie0_phy_rchng_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie0_phy_rchng_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie1_phy_rchng_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie1_phy_rchng_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_0_aux_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_0_aux_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_0_cfg_ahb_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_0_cfg_ahb_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_0_mstr_axi_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_0_mstr_axi_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_0_pipe_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_0_pipe_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_0_slv_axi_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_0_slv_axi_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_0_slv_q2a_axi_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_0_slv_q2a_axi_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_1_aux_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_1_aux_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_1_cfg_ahb_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_1_cfg_ahb_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_1_mstr_axi_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_1_mstr_axi_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_1_pipe_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_1_pipe_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_1_slv_axi_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_1_slv_axi_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_1_slv_q2a_axi_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_1_slv_q2a_axi_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_pcie_throttle_core_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_pcie_throttle_core_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_throttle_pcie_ahb_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gcc_throttle_pcie_ahb_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gcc_video_ahb_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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@ -897,11 +1057,31 @@ static struct clk_hw *debugcc_yupik_hws[] = {
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&measure_only_apcs_silver_post_acd_clk.hw,
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&measure_only_cnoc_clk.hw,
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&measure_only_disp_cc_xo_clk.hw,
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&measure_only_gcc_aggre_noc_pcie_0_axi_clk.hw,
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&measure_only_gcc_aggre_noc_pcie_1_axi_clk.hw,
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&measure_only_gcc_aggre_noc_pcie_center_sf_axi_clk.hw,
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&measure_only_gcc_camera_ahb_clk.hw,
|
||||
&measure_only_gcc_camera_xo_clk.hw,
|
||||
&measure_only_gcc_ddrss_pcie_sf_clk.hw,
|
||||
&measure_only_gcc_disp_ahb_clk.hw,
|
||||
&measure_only_gcc_disp_xo_clk.hw,
|
||||
&measure_only_gcc_gpu_cfg_ahb_clk.hw,
|
||||
&measure_only_gcc_pcie0_phy_rchng_clk.hw,
|
||||
&measure_only_gcc_pcie1_phy_rchng_clk.hw,
|
||||
&measure_only_gcc_pcie_0_aux_clk.hw,
|
||||
&measure_only_gcc_pcie_0_cfg_ahb_clk.hw,
|
||||
&measure_only_gcc_pcie_0_mstr_axi_clk.hw,
|
||||
&measure_only_gcc_pcie_0_pipe_clk.hw,
|
||||
&measure_only_gcc_pcie_0_slv_axi_clk.hw,
|
||||
&measure_only_gcc_pcie_0_slv_q2a_axi_clk.hw,
|
||||
&measure_only_gcc_pcie_1_aux_clk.hw,
|
||||
&measure_only_gcc_pcie_1_cfg_ahb_clk.hw,
|
||||
&measure_only_gcc_pcie_1_mstr_axi_clk.hw,
|
||||
&measure_only_gcc_pcie_1_pipe_clk.hw,
|
||||
&measure_only_gcc_pcie_1_slv_axi_clk.hw,
|
||||
&measure_only_gcc_pcie_1_slv_q2a_axi_clk.hw,
|
||||
&measure_only_gcc_pcie_throttle_core_clk.hw,
|
||||
&measure_only_gcc_throttle_pcie_ahb_clk.hw,
|
||||
&measure_only_gcc_video_ahb_clk.hw,
|
||||
&measure_only_gcc_video_xo_clk.hw,
|
||||
&measure_only_gpu_cc_cb_clk.hw,
|
||||
|
|
|
|||
Loading…
Reference in a new issue