mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
Merge branch 'locking-arch-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull arch atomic cleanups from Ingo Molnar:
"This is a series kept separate from the main locking tree, which
cleans up and improves various details in the atomics type handling:
- Remove the unused atomic_or_long() method
- Consolidate and compress atomic ops implementations between
architectures, to reduce linecount and to make it easier to add new
ops.
- Rewrite generic atomic support to only require cmpxchg() from an
architecture - generate all other methods from that"
* 'locking-arch-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
locking,arch: Use ACCESS_ONCE() instead of cast to volatile in atomic_read()
locking, mips: Fix atomics
locking, sparc64: Fix atomics
locking,arch: Rewrite generic atomic support
locking,arch,xtensa: Fold atomic_ops
locking,arch,sparc: Fold atomic_ops
locking,arch,sh: Fold atomic_ops
locking,arch,powerpc: Fold atomic_ops
locking,arch,parisc: Fold atomic_ops
locking,arch,mn10300: Fold atomic_ops
locking,arch,mips: Fold atomic_ops
locking,arch,metag: Fold atomic_ops
locking,arch,m68k: Fold atomic_ops
locking,arch,m32r: Fold atomic_ops
locking,arch,ia64: Fold atomic_ops
locking,arch,hexagon: Fold atomic_ops
locking,arch,cris: Fold atomic_ops
locking,arch,avr32: Fold atomic_ops
locking,arch,arm64: Fold atomic_ops
locking,arch,arm: Fold atomic_ops
...
This commit is contained in:
Linus Torvalds
commit
dbb885fecc
33 changed files with 1611 additions and 2320 deletions
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@ -25,79 +25,36 @@
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#define atomic_set(v, i) (((v)->counter) = (i))
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static inline void atomic_add(int i, atomic_t *v)
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{
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unsigned int temp;
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned int temp; \
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\
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__asm__ __volatile__( \
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"1: llock %0, [%1] \n" \
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" " #asm_op " %0, %0, %2 \n" \
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" scond %0, [%1] \n" \
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" bnz 1b \n" \
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: "=&r"(temp) /* Early clobber, to prevent reg reuse */ \
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: "r"(&v->counter), "ir"(i) \
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: "cc"); \
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} \
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" add %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp) /* Early clobber, to prevent reg reuse */
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: "r"(&v->counter), "ir"(i)
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: "cc");
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" sub %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(&v->counter), "ir"(i)
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: "cc");
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}
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/* add and also return the new value */
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" add %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(&v->counter), "ir"(i)
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: "cc");
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return temp;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" sub %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(&v->counter), "ir"(i)
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: "cc");
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return temp;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" bic %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(addr), "ir"(mask)
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: "cc");
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned int temp; \
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\
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__asm__ __volatile__( \
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"1: llock %0, [%1] \n" \
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" " #asm_op " %0, %0, %2 \n" \
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" scond %0, [%1] \n" \
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" bnz 1b \n" \
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: "=&r"(temp) \
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: "r"(&v->counter), "ir"(i) \
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: "cc"); \
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\
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return temp; \
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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@ -126,6 +83,7 @@ static inline void atomic_set(atomic_t *v, int i)
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v->counter = i;
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atomic_ops_unlock(flags);
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}
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#endif
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/*
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@ -133,63 +91,47 @@ static inline void atomic_set(atomic_t *v, int i)
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* Locking would change to irq-disabling only (UP) and spinlocks (SMP)
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*/
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static inline void atomic_add(int i, atomic_t *v)
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{
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unsigned long flags;
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atomic_ops_lock(flags);
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v->counter += i;
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atomic_ops_unlock(flags);
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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\
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atomic_ops_lock(flags); \
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v->counter c_op i; \
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atomic_ops_unlock(flags); \
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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unsigned long flags;
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atomic_ops_lock(flags);
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v->counter -= i;
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atomic_ops_unlock(flags);
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long flags;
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unsigned long temp;
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atomic_ops_lock(flags);
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temp = v->counter;
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temp += i;
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v->counter = temp;
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atomic_ops_unlock(flags);
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return temp;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long flags;
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unsigned long temp;
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atomic_ops_lock(flags);
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temp = v->counter;
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temp -= i;
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v->counter = temp;
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atomic_ops_unlock(flags);
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return temp;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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unsigned long flags;
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atomic_ops_lock(flags);
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*addr &= ~mask;
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atomic_ops_unlock(flags);
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#define ATOMIC_OP_RETURN(op, c_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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unsigned long temp; \
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\
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atomic_ops_lock(flags); \
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temp = v->counter; \
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temp c_op i; \
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v->counter = temp; \
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atomic_ops_unlock(flags); \
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\
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return temp; \
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}
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#endif /* !CONFIG_ARC_HAS_LLSC */
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, add)
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ATOMIC_OPS(sub, -=, sub)
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ATOMIC_OP(and, &=, and)
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#define atomic_clear_mask(mask, v) atomic_and(~(mask), (v))
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#undef ATOMIC_OPS
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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/**
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* __atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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