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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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mmc: sdhci-msm: dump vendor specific registers during error
Implement dump_vendor_registers host operation to print the vendor specific registers in addition to standard SDHC register during error conditions. Change-Id: Id0b322d0c7bf229c86dd9b290fcfc37208a4eafe Signed-off-by: Sahitya Tummala <stummala@codeaurora.org> Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
This commit is contained in:
Sarthak Garg
parent
5168327a4f
commit
dbeba97906
4 changed files with 158 additions and 1 deletions
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@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef LINUX_MMC_CQHCI_H
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#define LINUX_MMC_CQHCI_H
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@ -107,6 +107,12 @@
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/* command response argument */
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#define CQHCI_CRA 0x5C
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/*
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* Add new macro for updated CQ vendor specific
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* register address for SDHC v5.0 onwards.
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*/
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#define CQE_V5_VENDOR_CFG 0x900
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#define CQHCI_INT_ALL 0xF
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#define CQHCI_IC_DEFAULT_ICCTH 31
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#define CQHCI_IC_DEFAULT_ICTOVAL 1
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@ -171,6 +177,7 @@ struct cqhci_host {
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bool activated;
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bool waiting_for_idle;
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bool recovery_halt;
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bool offset_changed;
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size_t desc_size;
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size_t data_size;
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@ -28,6 +28,7 @@
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#define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
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#define CORE_VERSION_MINOR_MASK 0xff
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#define CORE_VERSION_TARGET_MASK 0x000000FF
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#define SDHCI_MSM_VER_420 0x49
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#define CORE_MCI_GENERICS 0x70
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#define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
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@ -103,6 +104,10 @@
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#define CORE_CDC_ERROR_CODE_MASK 0x7000000
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#define CQ_CMD_DBG_RAM 0x110
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#define CQ_CMD_DBG_RAM_WA 0x150
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#define CQ_CMD_DBG_RAM_OL 0x154
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#define CORE_CSR_CDC_GEN_CFG 0x178
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#define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
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#define CORE_CDC_SWITCH_RC_EN BIT(1)
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@ -405,6 +410,7 @@ struct sdhci_msm_host {
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unsigned long clk_rate;
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struct sdhci_msm_vreg_data *vreg_data;
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struct mmc_host *mmc;
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struct cqhci_host *cq_host;
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bool use_14lpp_dll_reset;
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bool tuning_done;
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bool calibration_done;
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@ -444,6 +450,7 @@ struct sdhci_msm_host {
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struct device_attribute pm_qos;
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u32 clk_gating_delay;
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u32 pm_qos_delay;
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bool cqhci_offset_changed;
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};
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static struct sdhci_msm_host *sdhci_slot[2];
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@ -3050,6 +3057,8 @@ static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
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msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
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cq_host->ops = &sdhci_msm_cqhci_ops;
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msm_host->cq_host = cq_host;
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cq_host->offset_changed = msm_host->cqhci_offset_changed;
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dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
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@ -3096,6 +3105,130 @@ static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
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sdhci_reset(host, mask);
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}
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#define MAX_TEST_BUS 60
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#define DRIVER_NAME "sdhci_msm"
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#define SDHCI_MSM_DUMP(f, x...) \
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pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
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#define DRV_NAME "cqhci-host"
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#if defined(CONFIG_SDC_QTI)
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static void sdhci_msm_cqe_dump_debug_ram(struct sdhci_host *host)
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{
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int i = 0;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_msm_offset *msm_offset = msm_host->offset;
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struct cqhci_host *cq_host;
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u32 version;
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u16 minor;
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int offset;
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if (msm_host->cq_host)
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cq_host = msm_host->cq_host;
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else
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return;
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version = msm_host_readl(msm_host, host,
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msm_offset->core_mci_version);
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minor = version & CORE_VERSION_TARGET_MASK;
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/* registers offset changed starting from 4.2.0 */
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offset = minor >= SDHCI_MSM_VER_420 ? 0 : 0x48;
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if (cq_host->offset_changed)
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offset += CQE_V5_VENDOR_CFG;
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pr_err("---- Debug RAM dump ----\n");
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pr_err(DRV_NAME ": Debug RAM wrap-around: 0x%08x | Debug RAM overlap: 0x%08x\n",
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cqhci_readl(cq_host, CQ_CMD_DBG_RAM_WA + offset),
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cqhci_readl(cq_host, CQ_CMD_DBG_RAM_OL + offset));
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while (i < 16) {
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pr_err(DRV_NAME ": Debug RAM dump [%d]: 0x%08x\n", i,
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cqhci_readl(cq_host, CQ_CMD_DBG_RAM + offset + (4 * i)));
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i++;
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}
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pr_err("-------------------------\n");
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}
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static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_msm_offset *msm_offset = msm_host->offset;
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int tbsel, tbsel2;
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int i, index = 0;
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u32 test_bus_val = 0;
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u32 debug_reg[MAX_TEST_BUS] = {0};
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SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n");
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if (msm_host->cq_host)
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sdhci_msm_cqe_dump_debug_ram(host);
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SDHCI_MSM_DUMP(
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"Data cnt: 0x%08x | Fifo cnt: 0x%08x | Int sts: 0x%08x\n",
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readl_relaxed(host->ioaddr + msm_offset->core_mci_data_cnt),
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readl_relaxed(host->ioaddr + msm_offset->core_mci_fifo_cnt),
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readl_relaxed(host->ioaddr + msm_offset->core_mci_status));
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SDHCI_MSM_DUMP(
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"DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n",
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readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
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readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
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readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
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SDHCI_MSM_DUMP(
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"DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n",
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readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
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readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
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readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
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SDHCI_MSM_DUMP(
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"SDCC ver: 0x%08x | Vndr adma err : addr0: 0x%08x addr1: 0x%08x\n",
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readl_relaxed(host->ioaddr + msm_offset->core_mci_version),
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readl_relaxed(host->ioaddr +
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msm_offset->core_vendor_spec_adma_err_addr0),
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readl_relaxed(host->ioaddr +
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msm_offset->core_vendor_spec_adma_err_addr1));
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SDHCI_MSM_DUMP(
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"Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
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readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
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readl_relaxed(host->ioaddr +
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msm_offset->core_vendor_spec_func2),
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readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
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/*
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* tbsel indicates [2:0] bits and tbsel2 indicates [7:4] bits
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* of core_testbus_config register.
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*
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* To select test bus 0 to 7 use tbsel and to select any test bus
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* above 7 use (tbsel2 | tbsel) to get the test bus number. For eg,
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* to select test bus 14, write 0x1E to core_testbus_config register
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* i.e., tbsel2[7:4] = 0001, tbsel[2:0] = 110.
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*/
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for (tbsel2 = 0; tbsel2 < 7; tbsel2++) {
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for (tbsel = 0; tbsel < 8; tbsel++) {
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if (index >= MAX_TEST_BUS)
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break;
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test_bus_val =
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(tbsel2 << msm_offset->core_testbus_sel2_bit) |
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tbsel | msm_offset->core_testbus_ena;
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writel_relaxed(test_bus_val, host->ioaddr +
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msm_offset->core_testbus_config);
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debug_reg[index++] = readl_relaxed(host->ioaddr +
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msm_offset->core_sdcc_debug_reg);
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}
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}
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for (i = 0; i < MAX_TEST_BUS; i = i + 4)
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SDHCI_MSM_DUMP(
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" Test bus[%d to %d]: 0x%08x 0x%08x 0x%08x 0x%08x\n",
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i, i + 3, debug_reg[i], debug_reg[i+1],
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debug_reg[i+2], debug_reg[i+3]);
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}
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#endif
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static const struct sdhci_msm_variant_ops mci_var_ops = {
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.msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
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.msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
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@ -3140,6 +3273,11 @@ static const struct sdhci_ops sdhci_msm_ops = {
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.get_max_clock = sdhci_msm_get_max_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
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#if defined(CONFIG_SDC_QTI)
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.dump_vendor_regs = sdhci_msm_dump_vendor_regs,
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#endif
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.write_w = sdhci_msm_writew,
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.write_b = sdhci_msm_writeb,
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.irq = sdhci_msm_cqe_irq,
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@ -3988,6 +4126,13 @@ static int sdhci_msm_probe(struct platform_device *pdev)
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if (core_major == 1 && core_minor >= 0x49)
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msm_host->updated_ddr_cfg = true;
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/* For SDHC v5.0.0 onwards, ICE 3.0 specific registers are added
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* in CQ register space, due to which few CQ registers are
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* shifted. Set cqhci_offset_changed boolean to use updated address.
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*/
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if (core_major == 1 && core_minor >= 0x6B)
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msm_host->cqhci_offset_changed = true;
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/*
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* Power on reset state may trigger power irq if previous status of
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* PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
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@ -110,7 +110,11 @@ void sdhci_dumpregs(struct sdhci_host *host)
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}
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#if defined(CONFIG_SDC_QTI)
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host->mmc->err_occurred = true;
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if (host->ops->dump_vendor_regs)
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host->ops->dump_vendor_regs(host);
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#endif
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SDHCI_DUMP("============================================\n");
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}
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EXPORT_SYMBOL_GPL(sdhci_dumpregs);
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@ -660,6 +660,7 @@ struct sdhci_ops {
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struct mmc_request *mrq);
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#if defined(CONFIG_SDC_QTI)
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unsigned int (*get_current_limit)(struct sdhci_host *host);
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void (*dump_vendor_regs)(struct sdhci_host *host);
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#endif
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};
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