From f60812099e370f90fb6430b6f54e9c7040504322 Mon Sep 17 00:00:00 2001 From: Chris Goldsworthy Date: Thu, 17 Oct 2019 18:45:17 -0700 Subject: [PATCH] iommu/arm-smmu: report BID, PID and MID of client on context fault Aid debugging by reporting the BID, PID and MID of a transaction during a context fault, in order to identify the master that initiated the fautling transaction. Change-Id: I2bed2b472a754f13bf85e3b576f0bf079d9d5541 Signed-off-by: Chris Goldsworthy --- drivers/iommu/arm-smmu.c | 11 ++++++++++- drivers/iommu/arm-smmu.h | 4 ++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 8d66db962474..e952425435fa 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1354,6 +1354,11 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) dev_dbg(smmu->dev, "Context fault handled by client: iova=0x%08lx, cb=%d, fsr=0x%x, fsynr0=0x%x, fsynr1=0x%x\n", iova, cfg->cbndx, fsr, fsynr0, fsynr1); + dev_dbg(smmu->dev, + "Client info: BID=0x%x, PID=0x%x, MID=0x%x\n", + FIELD_GET(FSYNR1_BID, fsynr1), + FIELD_GET(FSYNR1_PID, fsynr1), + FIELD_GET(FSYNR1_MID, fsynr1)); dev_dbg(smmu->dev, "soft iova-to-phys=%pa\n", &phys_soft); ret = IRQ_HANDLED; @@ -1367,7 +1372,11 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) dev_err(smmu->dev, "Unhandled context fault: iova=0x%08lx, cb=%d, fsr=0x%x, fsynr0=0x%x, fsynr1=0x%x\n", iova, cfg->cbndx, fsr, fsynr0, fsynr1); - + dev_err(smmu->dev, + "Client info: BID=0x%x, PID=0x%x, MID=0x%x\n", + FIELD_GET(FSYNR1_BID, fsynr1), + FIELD_GET(FSYNR1_PID, fsynr1), + FIELD_GET(FSYNR1_MID, fsynr1)); dev_err(smmu->dev, "soft iova-to-phys=%pa\n", &phys_soft); diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index 4c12ca09ab9d..da20bf61d219 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -211,6 +211,10 @@ enum arm_smmu_cbar_type { #define FSYNR0_WNR BIT(4) #define ARM_SMMU_CB_FSYNR1 0x6c +#define FSYNR1_BID GENMASK(15, 13) +#define FSYNR1_PID GENMASK(12, 8) +#define FSYNR1_MID GENMASK(7, 0) + #define ARM_SMMU_CB_S1_TLBIVA 0x600 #define ARM_SMMU_CB_S1_TLBIASID 0x610 #define ARM_SMMU_CB_S1_TLBIALL 0x618