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fw-api: Fix E3.0: E3R44: WCSS_VERSION 2544

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Incremental hw header file update to fix compilation errors.

Change-Id: I9c101255444ca892e1a6006a55f11c0de0fbffb4
CRs-Fixed: 3580269
This commit is contained in:
Prakash Manjunathappa 2023-07-12 16:47:18 -07:00 • committed by Rahul Choudhary
commit dc56b9d07a
5 changed files with 66 additions and 53 deletions
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80
hw/peach/v1/phyrx_rssi_legacy.h
View file

@ -58,55 +58,55 @@ struct phyrx_rssi_legacy {
#endif
};
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x0000000f
#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x00000000
#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0
#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3
#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x0000000f
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x00000010
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x00000010
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000e0
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x00000000
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x000000e0
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x00000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x0000ff00
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x00000000
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x0000ff00
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x00000000
#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16
#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31
#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0xffff0000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 0
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 31
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 0
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 31
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 0
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 7
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff
#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c
#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 0
#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 7
#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 8
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 8
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x00000100
#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c
#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_LSB 8
#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MSB 8
#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MASK 0x00000100
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000c
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 9
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 31
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe00
#define PHYRX_RSSI_LEGACY_RESERVED_3A_OFFSET 0x0000000c
#define PHYRX_RSSI_LEGACY_RESERVED_3A_LSB 9
#define PHYRX_RSSI_LEGACY_RESERVED_3A_MSB 31
#define PHYRX_RSSI_LEGACY_RESERVED_3A_MASK 0xfffffe00
#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x00000010
#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0

4
hw/peach/v1/rx_msdu_desc_info.h
View file

@ -38,9 +38,9 @@ struct rx_msdu_desc_info {
intra_bss : 1,
dest_chip_id : 2,
decap_format : 2,
__reserved_g_0015 : 1;
reserved_0a : 1;
#else
uint32_t __reserved_g_0015 : 1,
uint32_t reserved_0a : 1,
decap_format : 2,
dest_chip_id : 2,
intra_bss : 1,

5
hw/peach/v1/rx_msdu_details.h
View file

@ -135,6 +135,11 @@ struct rx_msdu_details {
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4

7
hw/peach/v1/uniform_descriptor_header.h
View file

@ -14,7 +14,6 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
#define _UNIFORM_DESCRIPTOR_HEADER_H_
@ -49,8 +48,12 @@ struct uniform_descriptor_header {
#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
/* RESERVED is overlapping with TX_MPDU_QUEUE_NUMBER
* TX_MPDU_QUEUE_NUMBER valid on in Buffer_type is any of Transmit_MPDU_*_descriptor
* Where as RESERVED is only used for debugging in REO_QUEUE_Descr reo_queue_desc
*/
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000

5
hw/peach/v1/wcss_seq_hwioreg_umac.h
View file

@ -803,6 +803,11 @@
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x548)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x54c)
#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x550)
#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x574)
#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16
#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f
#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x554)
#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x558)
#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x55c)