From dc5c49e32cb981bc633f837b54268c7403ee3455 Mon Sep 17 00:00:00 2001
From: Vivek Kumar <vivekuma@qti.qualcomm.com>
Date: Tue, 19 May 2020 17:25:20 +0530
Subject: [PATCH] ARM: dts: msm: Add device node for llcc on sm8150

Add device node for last level cache controller
on SM8150.

Change-Id: I408fa74757a016ac57263f292a14e134bab33697
---
 bindings/arm/msm/qcom,llcc.txt | 2 +-
 qcom/sm8150.dtsi               | 7 +++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt
index 64e1fe37e270..c7640f8bf122 100644
--- a/bindings/arm/msm/qcom,llcc.txt
+++ b/bindings/arm/msm/qcom,llcc.txt
@@ -13,7 +13,7 @@ Properties:
 	Value type: <string>
 	Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc"
 	            or "qcom,shima-llcc" or "qcom,sdxlemur-llcc"
-	            or "qcom,yupik-llcc"
+	            or "qcom,yupik-llcc" or "qcom,sm8150-llcc"
 		    "qcom,llcc-v2" must be appended for V2 hardware.
 
 - reg:
diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi
index 2825173ad88c..fe7a0251dfd2 100644
--- a/qcom/sm8150.dtsi
+++ b/qcom/sm8150.dtsi
@@ -1950,6 +1950,13 @@
 		qcom,firmware-name = "venus";
 		memory-region = <&pil_video_mem>;
 	};
+
+	cache-controller@9200000 {
+		compatible = "qcom,sm8150-llcc";
+		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
+		reg-names = "llcc_base", "llcc_broadcast_base";
+		cap-based-alloc-and-pwr-collapse;
+	};
 };
 
 &firmware {