From dc86c37e427741ab295a4f83bbadff84e95dd42a Mon Sep 17 00:00:00 2001 From: Konstantin Makariev Date: Mon, 1 Mar 2021 19:11:17 -0600 Subject: [PATCH] bos0614_mmi: added features Added the following features: 1) BOS0614 registers dump sysfs 2) reading device tree and applying default config in case of power cut Change-Id: I53f1b7069ea4d74aa8b02ac525765951fe29bcce Signed-off-by: Konstantin Makariev Reviewed-on: https://gerrit.mot.com/1889879 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Ling Jin Submit-Approved: Jira Key --- drivers/input/misc/bos0614_mmi/bosDriver.c | 253 +- drivers/input/misc/bos0614_mmi/i2cLinux.c | 142 +- drivers/input/misc/bos0614_mmi/i2cLinux.h | 23 + .../dk-core/contribs/cmsis/.gitattributes | 21 - .../libs/dk-core/contribs/cmsis/.gitignore | 10 - .../dk-core/contribs/cmsis/ARM.CMSIS.pdsc | 4073 ----------------- .../libs/dk-core/contribs/cmsis/manifest | 50 - .../src/bsp/drivers/haptic/bos0614Driver.c | 185 +- .../src/bsp/drivers/haptic/bos0614Driver.h | 1 + 9 files changed, 384 insertions(+), 4374 deletions(-) delete mode 100644 drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/.gitattributes delete mode 100644 drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/.gitignore delete mode 100644 drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/ARM.CMSIS.pdsc delete mode 100644 drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/manifest diff --git a/drivers/input/misc/bos0614_mmi/bosDriver.c b/drivers/input/misc/bos0614_mmi/bosDriver.c index 8c9c12c9cb66..e5d51b96f5f2 100644 --- a/drivers/input/misc/bos0614_mmi/bosDriver.c +++ b/drivers/input/misc/bos0614_mmi/bosDriver.c @@ -21,6 +21,10 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. // +#define pr_fmt(fmt) "bos0614: %s: " fmt, __func__ + +#define DEBUG +//#undef DEBUG #include #include @@ -34,62 +38,12 @@ #include "libs/dk-core/src/bsp/drivers/i2c/i2c.h" #include "libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.h" -enum { - PARAM_UCHAR8 = 1, - PARAM_INT16, - PARAM_UINT16, - PARAM_INT32, - PARAM_UINT32 -}; - -typedef struct { - int tid; - void *data_ptr; -} ParamsLst; - -#define PARAM_ADD(t, v) {\ - params[numP].tid = t;\ - params[numP].data_ptr = v;\ - numP++;\ -} - -static int process_params(ParamsLst *params, int numP, const char *buffer) -{ - char *arg, *buf, *p; - int n, err; - - buf = kstrdup(buffer, GFP_KERNEL); - for (n = 0; n < numP && p && *p; n++, params++) { - arg = strsep(&p, " "); - if (!arg || !*arg) - break; - - switch (params->tid) { - case PARAM_UCHAR8: - err = kstrtou8(arg, 0, params->data_ptr); - break; - case PARAM_INT16: - err = kstrtos16(arg, 0, params->data_ptr); - break; - case PARAM_UINT16: - err = kstrtou16(arg, 0, params->data_ptr); - break; - case PARAM_INT32: - err = kstrtoint(arg, 0, params->data_ptr); - break; - case PARAM_UINT32: - err = kstrtouint(arg, 0, params->data_ptr); - break; - } - - if (err) { - n = err; - break; - } - } - kfree(buf); - return n; -} +#ifdef DEBUG +#undef pr_debug +#define pr_debug pr_err +#undef dev_dbg +#define dev_dbg dev_info +#endif typedef struct { @@ -132,6 +86,40 @@ static ssize_t getChipId(struct device *dev, static DEVICE_ATTR(chip_id, 0440, getChipId, NULL); +static ssize_t getRegsDump(struct device *dev, + struct device_attribute *attr, char *buf) +{ + Context *ctx = dev_get_drvdata(dev); + ssize_t blen = 0; + (void) attr; + + if (ctx != NULL) + { + mutex_lock(&ctx->lock); + + if (ctx->hapticDriver != NULL) + { + bool res; + u16 r, rval; + /* dump first 42 registers */ + for (r = 0; r < ADDRESS_BOS0614_BIST_REG; r++) { + rval = 0x2bad; + res = ctx->hapticDriver->getRegister(ctx->hapticDriver, r, &rval); + blen += snprintf(buf + blen, PAGE_SIZE - blen, + "%02X: 0x%02X 0x%02X\n", r, + (rval & 0xFF00) >> 8, + (rval & 0x00FF)); + } + } + + mutex_unlock(&ctx->lock); + } + + return blen; +} + +static DEVICE_ATTR(regs, 0440, getRegsDump, NULL); + static bool hasError(BOSError *errors, size_t length, BOSError errorType) { size_t index; @@ -161,18 +149,19 @@ static ssize_t getIcErrors(struct device *dev, if (ctx != NULL && ctx->hapticDriver != NULL) { + HapticDriver *driver = ctx->hapticDriver; + size_t nbrErros; BOSError *errors; + errors = kzalloc(sizeof(BOSError) * BOSERROR_Length, GFP_KERNEL); + if (!errors) + return res; + mutex_lock(&ctx->lock); - errors = kzalloc(sizeof(BOSError) * BOSERROR_Length, GFP_KERNEL); + nbrErros = driver->getError(driver, errors, BOSERROR_Length); - if (errors != NULL) - { - HapticDriver *driver = ctx->hapticDriver; - size_t nbrErros = driver->getError(driver, errors, BOSERROR_Length); - - res = snprintf(buf, PAGE_SIZE, "SC: %d UVLO: %d IDAC: %d MAX_POWER: %d OVT: %d OVV: %d\n", + res = snprintf(buf, PAGE_SIZE, "SC: %d UVLO: %d IDAC: %d MAX_POWER: %d OVT: %d OVV: %d\n", hasError(errors, nbrErros, BOSERROR_SHORT_CIRCUIT), hasError(errors, nbrErros, BOSERROR_UVLO), hasError(errors, nbrErros, BOSERROR_IDAC), @@ -180,9 +169,7 @@ static ssize_t getIcErrors(struct device *dev, hasError(errors, nbrErros, BOSERROR_OVT), hasError(errors, nbrErros, BOSERROR_OVV)); - kfree(errors); - } - + kfree(errors); mutex_unlock(&ctx->lock); } @@ -202,6 +189,7 @@ static ssize_t setSynthWaveform(struct device *dev, if (ctx != NULL && ctx->hapticDriver != NULL) { + HapticDriver *driver = ctx->hapticDriver; WaveformId id = 0; uint8_t startSliceId = 0; size_t nbrOfSlices = 0; @@ -209,7 +197,7 @@ static ssize_t setSynthWaveform(struct device *dev, uint8_t outputChannel = 0; size_t paramLength = 0; int numP = 0; - ParamsLst params[5]; + ParamsLst params[SET_WAVEFORM_PARAM_LENGTH]; PARAM_ADD(PARAM_UCHAR8, &id); PARAM_ADD(PARAM_UCHAR8, &startSliceId); @@ -217,27 +205,20 @@ static ssize_t setSynthWaveform(struct device *dev, PARAM_ADD(PARAM_UINT16, &cycle); PARAM_ADD(PARAM_UCHAR8, &outputChannel); - mutex_lock(&ctx->lock); - paramLength = process_params(params, numP, buf); - if (paramLength < 0) { - mutex_unlock(&ctx->lock); + if (paramLength != SET_WAVEFORM_PARAM_LENGTH) { return (ssize_t)paramLength; } - //paramLength = sscanf(buf, "%hh %hi %zi %hi %hi", &id, &startSliceId, - // &nbrOfSlices, &cycle, &outputChannel); + dev_dbg(ctx->dev, "[Set Synth Waveform] Waveform Id: %d Start Slice Id: %d Nbr Of Slices: %zu Cycle: %d Output Channel: %d\n", id, startSliceId, nbrOfSlices, cycle, outputChannel); - if (paramLength == SET_WAVEFORM_PARAM_LENGTH) - { - HapticDriver *driver = ctx->hapticDriver; + mutex_lock(&ctx->lock); - if (driver->synthSetWaveform(driver, id, startSliceId, nbrOfSlices, cycle, outputChannel)) - { - res = count; - } + if (driver->synthSetWaveform(driver, id, startSliceId, nbrOfSlices, cycle, outputChannel)) + { + res = count; } mutex_unlock(&ctx->lock); @@ -258,35 +239,31 @@ static ssize_t setSynthSlice(struct device *dev, if (ctx != NULL && ctx->hapticDriver != NULL) { - HapticDriver *driver; + HapticDriver *driver = ctx->hapticDriver; SynthSlice slice; uint8_t outputChannel = 0; size_t paramLength = 0; int numP = 0; - ParamsLst params[4]; + ParamsLst params[SET_SLICE_PARAM_LENGTH]; PARAM_ADD(PARAM_UINT32, &slice.sliceId); PARAM_ADD(PARAM_INT32, &slice.mVAmp); PARAM_ADD(PARAM_UINT32, &slice.mHzFreq); + PARAM_ADD(PARAM_UINT32, &slice.cycle); PARAM_ADD(PARAM_UCHAR8, &outputChannel); - mutex_lock(&ctx->lock); - - driver = ctx->hapticDriver; - paramLength = process_params(params, numP, buf); - if (paramLength < 0) { - mutex_unlock(&ctx->lock); + if (paramLength != SET_SLICE_PARAM_LENGTH) { return (ssize_t)paramLength; } - //paramLength = sscanf(buf, "%d %d %d %d %d", &slice.sliceId, &slice.mVAmp, - // &slice.mHzFreq, &slice.cycle, &outputChannel); + dev_dbg(ctx->dev, "[Set Slice] Slice Id: %d Amplitude: %d mV Frequency: %d milliHertz Cycle: %d Output Channel: %d\n", slice.sliceId, slice.mVAmp, slice.mHzFreq, slice.cycle, outputChannel); - if (paramLength == SET_SLICE_PARAM_LENGTH && - driver->synthSetSlice(driver, (const SynthSlice *) &slice, outputChannel)) + mutex_lock(&ctx->lock); + + if (driver->synthSetSlice(driver, (const SynthSlice *) &slice, outputChannel)) { res = count; } @@ -310,26 +287,24 @@ static ssize_t synthPlay(struct device *dev, if (ctx != NULL && ctx->hapticDriver != NULL) { - HapticDriver *driver; + HapticDriver *driver = ctx->hapticDriver; WaveformId start = 0; WaveformId stop = 0; size_t paramLength = 0; int numP = 0; - ParamsLst params[2]; + ParamsLst params[SYNTH_PLAY_PARAM_LENGTH]; PARAM_ADD(PARAM_UCHAR8, &start); PARAM_ADD(PARAM_UCHAR8, &stop); - driver = ctx->hapticDriver; - paramLength = process_params(params, numP, buf); - if (paramLength < 0) { - mutex_unlock(&ctx->lock); + if (paramLength != SYNTH_PLAY_PARAM_LENGTH) { return (ssize_t)paramLength; } - //paramLength = sscanf(buf, "%hi %hi", &start, &stop); - if (paramLength == SYNTH_PLAY_PARAM_LENGTH && driver->wfsPlay(driver, start, stop)) + mutex_lock(&ctx->lock); + + if (driver->wfsPlay(driver, start, stop)) { res = count; } @@ -352,27 +327,25 @@ static ssize_t setOutput(struct device *dev, if (ctx != NULL && ctx->hapticDriver != NULL) { - HapticDriver *driver; + HapticDriver *driver = ctx->hapticDriver; int outputState = 0; size_t paramLength = 0; - bool bOutputState = outputState > 0 ? true : false; + bool bOutputState; int numP = 0; - ParamsLst params[1]; + ParamsLst params[CTRL_OUTPUT_PARAM_LENGTH]; PARAM_ADD(PARAM_INT32, &outputState); - mutex_lock(&ctx->lock); - driver = ctx->hapticDriver; - paramLength = process_params(params, numP, buf); - if (paramLength < 0) { - mutex_unlock(&ctx->lock); + if (paramLength != CTRL_OUTPUT_PARAM_LENGTH) { return (ssize_t)paramLength; } - //paramLength = sscanf(buf, "%d", &outputState); - if (paramLength == CTRL_OUTPUT_PARAM_LENGTH && - driver->ctrlOutput(driver, bOutputState)) + bOutputState = outputState > 0 ? true : false; + + mutex_lock(&ctx->lock); + + if (driver->ctrlOutput(driver, bOutputState)) { dev_dbg(ctx->dev, "[Set Output] State: %d \n", bOutputState); @@ -440,37 +413,33 @@ static ssize_t setSensingConfig(struct device *dev, if (ctx != NULL && ctx->hapticDriver != NULL) { - HapticDriver *driver; + HapticDriver *driver = ctx->hapticDriver; SensingConfig config; ChannelId channelId = 0; size_t paramLength = 0; - const char *directionS = getSensingDirection(config.direction); - const char *modeS = getSensingDetectionMode(config.mode); + const char *directionS; + const char *modeS; int numP = 0; - ParamsLst params[6]; + ParamsLst params[SENSING_CONFIG_PARAM_LENGTH]; PARAM_ADD(PARAM_UCHAR8, &channelId); PARAM_ADD(PARAM_UCHAR8, &config.mode); PARAM_ADD(PARAM_UCHAR8, &config.direction); PARAM_ADD(PARAM_UINT16, &config.debounceUs); - PARAM_ADD(PARAM_UINT16, &config.thresholdMv); + PARAM_ADD(PARAM_INT16, &config.thresholdMv); PARAM_ADD(PARAM_UCHAR8, &config.stabilisationMs); - mutex_lock(&ctx->lock); - driver = ctx->hapticDriver; - paramLength = process_params(params, numP, buf); - if (paramLength < 0) { - mutex_unlock(&ctx->lock); + if (paramLength != SENSING_CONFIG_PARAM_LENGTH) { return (ssize_t)paramLength; } - //paramLength = sscanf(buf, "%hhu %d %d %hd %hd %s", &channelId, &config.mode, - // &config.direction, &config.debounceUs, - // &config.thresholdMv, &config.stabilisationMs); - if (paramLength == SENSING_CONFIG_PARAM_LENGTH && - directionS != NULL && - modeS != NULL && + directionS = getSensingDirection(config.direction); + modeS = getSensingDetectionMode(config.mode); + + mutex_lock(&ctx->lock); + + if (directionS != NULL && modeS != NULL && driver->configSensing(driver, channelId, config) && ctx->hapticDriver->configGPO(ctx->hapticDriver, channelId, GPO_ButtonState)) { @@ -499,32 +468,29 @@ static ssize_t setSensingAutoPlay(struct device *dev, if (ctx != NULL && ctx->hapticDriver != NULL) { - HapticDriver *driver; + HapticDriver *driver = ctx->hapticDriver; ChannelId channelId = 0; WaveformId id = 0; SensingDirection direction = 0; size_t paramLength = 0; const char *directionS; int numP = 0; - ParamsLst params[3]; + ParamsLst params[SENSING_AUTO_FEEDBACK_PARAM_LENGTH]; PARAM_ADD(PARAM_UCHAR8, &channelId); PARAM_ADD(PARAM_UCHAR8, &id); PARAM_ADD(PARAM_UCHAR8, &direction); paramLength = process_params(params, numP, buf); - if (paramLength < 0) { + if (paramLength != SENSING_AUTO_FEEDBACK_PARAM_LENGTH) { return (ssize_t)paramLength; } - //paramLength = sscanf(buf, "%d %d %d", &channelId, &id, &direction); directionS = getSensingDirection(direction); mutex_lock(&ctx->lock); - driver = ctx->hapticDriver; - if (paramLength == SENSING_AUTO_FEEDBACK_PARAM_LENGTH && - directionS != NULL && + if (directionS != NULL && driver->sensingAutoPlayWave(driver, channelId, id, direction)) { dev_dbg(ctx->dev, "[Set Sensing Automatic Feedback] Channel #: %d Waveform #: %d Direction: %s", channelId, @@ -551,29 +517,27 @@ static ssize_t stopSensing(struct device *dev, if (ctx != NULL && ctx->hapticDriver != NULL) { - HapticDriver *driver; + HapticDriver *driver = ctx->hapticDriver; ChannelId channelId = 0; SensingDirection direction = 0; const char *directionS; size_t paramLength = 0; int numP = 0; - ParamsLst params[2]; + ParamsLst params[STOP_SENSING_PARAM_LENGTH]; PARAM_ADD(PARAM_UCHAR8, &channelId); PARAM_ADD(PARAM_UCHAR8, &direction); paramLength = process_params(params, numP, buf); - if (paramLength < 0) { + if (paramLength != STOP_SENSING_PARAM_LENGTH) { return (ssize_t)paramLength; } - //paramLength = sscanf(buf, "%d %d", &channelId, &direction); + directionS = getSensingDirection(direction); mutex_lock(&ctx->lock); - driver = ctx->hapticDriver; - if (paramLength == STOP_SENSING_PARAM_LENGTH && - directionS != NULL && + if (directionS != NULL && driver->stopSensing(driver, channelId, direction)) { dev_dbg(ctx->dev, "[Remove Sensing Profile] Channel #: %d Direction: %s", channelId, directionS); @@ -592,6 +556,7 @@ static DEVICE_ATTR(sensing_stop, 0220, NULL, stopSensing); static struct attribute *bosDriverAttrs[] = { &dev_attr_chip_id.attr, + &dev_attr_regs.attr, &dev_attr_set_waveform.attr, &dev_attr_set_slice.attr, &dev_attr_synth_play.attr, @@ -666,6 +631,8 @@ static int bosDriverI2cProbe(struct i2c_client *client, resource.i2c = ctx->i2c; ctx->hapticDriver = bos0614DriverI2cInit(resource); + pr_debug("i2c: %p, driver: %p\n", ctx->i2c, ctx->hapticDriver); + if (ctx->i2c == NULL || ctx->hapticDriver == NULL) { dev_err(&client->dev, "Failed to instantiate BOS0614 driver\n"); @@ -757,13 +724,13 @@ static struct i2c_driver bosDriverI2c = { #ifdef CONFIG_OF static int __init bosDriver_init(void) { - pr_info("%s: loading driver\n", __func__); + pr_debug("loading driver\n"); return i2c_add_driver(&bosDriverI2c); } static void __exit bosDriver_exit(void) { - pr_info("%s: removing driver\n", __func__); + pr_debug("removing driver\n"); i2c_del_driver(&bosDriverI2c); } diff --git a/drivers/input/misc/bos0614_mmi/i2cLinux.c b/drivers/input/misc/bos0614_mmi/i2cLinux.c index 358f72d9cc98..777b7f1e4c29 100644 --- a/drivers/input/misc/bos0614_mmi/i2cLinux.c +++ b/drivers/input/misc/bos0614_mmi/i2cLinux.c @@ -21,6 +21,11 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. // +#define pr_fmt(fmt) "bos0614: %s: " fmt, __func__ + +#define DEBUG +//#undef DEBUG + #include #include #include @@ -28,6 +33,13 @@ #include "i2cLinux.h" +#ifdef DEBUG +#undef pr_debug +#define pr_debug pr_err +#undef dev_dbg +#define dev_dbg dev_err +#endif + typedef struct { I2c driver; @@ -39,6 +51,124 @@ static void initDriverFct(Context *ctx); #define NBR_CHAR_PER_BYTE (5) #define ESCAPE_CHAR (1) +int process_params(ParamsLst *params, int numP, const char *buffer) +{ + char *arg, *buf, *p; + int n, err; + unsigned int value; + + p = buf = kstrdup(buffer, GFP_KERNEL); + for (n = 0; n < numP && p && *p; n++, params++) { + arg = strsep(&p, " "); + if (!arg || !*arg) + break; + + pr_debug("arg=[%s] rest=[%s]\n", arg, p); + + switch (params->tid) { + case PARAM_UCHAR8: + err = kstrtou8(arg, 0, params->data_ptr); + value = (unsigned int)*(unsigned char *)params->data_ptr; + break; + case PARAM_INT16: + err = kstrtos16(arg, 0, params->data_ptr); + value = (unsigned int)*(short *)params->data_ptr; + break; + case PARAM_UINT16: + err = kstrtou16(arg, 0, params->data_ptr); + value = (unsigned int)*(unsigned short *)params->data_ptr; + break; + case PARAM_INT32: + err = kstrtoint(arg, 0, params->data_ptr); + value = (unsigned int)*(int *)params->data_ptr; + break; + case PARAM_UINT32: + err = kstrtouint(arg, 0, params->data_ptr); + value = *(unsigned int *)params->data_ptr; + break; + } + + if (err) { + n = err; + break; + } else + pr_debug("[%d]=%u\n", n, value); + } + kfree(buf); + pr_debug("processed %d input parameters\n", n); + return n; +} +#if 0 +static int readRegsConfig(Context *ctx, struct device_node *parent, const char *suffix) +{ + Bos0614RegisterStruct *config = getAllRegsPtr(); + struct device_node *node; + char node_name[64]; + u32 *temp, length = 0; + int npairs, i, index, ret = -EIO; + + scnprintf(node_name, 63, "config-%s", suffix); + node = of_find_node_by_name(parent, node_name); + if (!node) + return -ENODEV; + + if (!of_find_property(node, "config-data", &length)) { + dev_err(&ctx->client->dev, "(config-%s) prop config-data not found\n", suffix); + goto out; + } + + npairs = length / 2; + dev_info(&ctx->client->dev, "(config-%s) array size %d\n", suffix, npairs); + + temp = kzalloc(length, GFP_KERNEL); + if (!temp) + goto out; + + ret = of_property_read_u32_array(node, "config-data", temp, sizeof(u32) * npairs * 2); + if (ret) { + dev_err(&ctx->client->dev, "error reading config-data (config-%s)\n", suffix); + goto release_mem; + } + + for (i = 0; i < npairs; i++) { + index =(uint16_t)*temp++; + config[index].value = (uint16_t)*temp++; + dev_info(&ctx->client->dev, "[%d] addr=0x%02x, val=0x%04x\n", + i, config[index].addr, config[index].value); + } + +release_mem: + kfree(temp); +out: + of_node_put(node); + + return ret; +} + +static int readDevTree(Context *ctx) +{ + int ret, verno; + struct device_node *np = ctx->client->dev.of_node; + struct device_node *config_np; + + config_np = of_find_node_by_name(np, "configs"); + if (!config_np) { + dev_info(&ctx->client->dev, "does not support configs\n"); + return 0; + } + + if (!of_property_read_u32(config_np, "config-ver", &verno)) + dev_info(&ctx->client->dev, "dt config Rev.%u\n", verno); + + ret = readRegsConfig(ctx, config_np, "default"); + if (ret > 0) + dev_info(&ctx->client->dev, "has default config\n"); + + of_node_put(config_np); + + return 0; +} +#endif static void logBuffer(const char *message, const void *data, size_t length) { size_t bufferLength = length * NBR_CHAR_PER_BYTE + ESCAPE_CHAR; @@ -57,15 +187,13 @@ static void logBuffer(const char *message, const void *data, size_t length) ptr += sprintf(ptr, index < (length - 1) ? "0x%02x " : "0x%02x", _data[index]); } - //printk("%s length: %zu [%s]\n", message, length, buf, bufferLength, ptr, end); - printk("%s length: %zu [%s]\n", message, length, buf); + pr_debug("%s length: %zu [%s]\n", message, length, buf); kfree(buf); } } - /* * Private Section */ @@ -142,16 +270,20 @@ I2c *i2cBoreasLinuxInit(struct i2c_client *client) { Context *ctx = kzalloc(sizeof(Context), GFP_KERNEL); - printk("[PF-Debug] I2C Client %p", client); - if (ctx != NULL) { ctx->client = client; initDriverFct(ctx); driver = &ctx->driver; +#if 0 + if (ctx->client->dev.of_node) + readDevTree(ctx); +#endif } } + pr_debug("I2C client: %p, driver: %p\n", client, driver); + return driver; } diff --git a/drivers/input/misc/bos0614_mmi/i2cLinux.h b/drivers/input/misc/bos0614_mmi/i2cLinux.h index a2511b4f2d37..a4e14076a352 100644 --- a/drivers/input/misc/bos0614_mmi/i2cLinux.h +++ b/drivers/input/misc/bos0614_mmi/i2cLinux.h @@ -25,8 +25,31 @@ #ifndef BOREAS_HAPTIC_DRIVER_LINUX_I2CLINUX_H #define BOREAS_HAPTIC_DRIVER_LINUX_I2CLINUX_H +#include #include #include "libs/dk-core/src/bsp/drivers/i2c/i2c.h" +#include "libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.h" + +enum { + PARAM_UCHAR8 = 1, + PARAM_INT16, + PARAM_UINT16, + PARAM_INT32, + PARAM_UINT32 +}; + +typedef struct { + int tid; + void *data_ptr; +} ParamsLst; + +#define PARAM_ADD(t, v) {\ + params[numP].tid = t;\ + params[numP].data_ptr = v;\ + numP++;\ +} + +int process_params(ParamsLst *params, int numP, const char *buffer); I2c *i2cBoreasLinuxInit(struct i2c_client *client); diff --git a/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/.gitattributes b/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/.gitattributes deleted file mode 100644 index 939926f67f78..000000000000 --- a/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/.gitattributes +++ /dev/null @@ -1,21 +0,0 @@ -# Set the default behavior, in case people don't have core.autocrlf set. -* text=auto -# Explicitly declare text files you want to always be normalized and converted -# to native line endings on checkout. -*.c text -*.h text -*.txt text -*.xsd text -*.pdsc text -*.svd text -*.bat text -# Declare files that will always have CRLF line endings on checkout. -*.uvproj text eol=crlf -*.uvproj text eol=crlf -# Denote all files that are truly binary and should not be modified. -*.png binary -*.jpg binary -*.a filter=lfs diff=lfs merge=lfs -text -*.lib filter=lfs diff=lfs merge=lfs -text -*.exe filter=lfs diff=lfs merge=lfs -text -CMSIS/Utilities/Linux-gcc-*/* filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/.gitignore b/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/.gitignore deleted file mode 100644 index 1cd4decf642c..000000000000 --- a/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/.gitignore +++ /dev/null @@ -1,10 +0,0 @@ -*.breadcrumb -*.junit -**/__pycache__ -Local_Release/ -CMSIS/Documentation/ -CMSIS/RTOS2/RTX/Library/ARM/MDK/RTX_CM.uvguix.* -CMSIS/CoreValidation/Tests/build -CMSIS/CoreValidation/Tests/bootloader/build -*.uvguix.* -*.uvmpw.uvgui.* diff --git a/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/ARM.CMSIS.pdsc b/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/ARM.CMSIS.pdsc deleted file mode 100644 index 90f584579836..000000000000 --- a/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/ARM.CMSIS.pdsc +++ /dev/null @@ -1,4073 +0,0 @@ - - - - CMSIS - CMSIS (Cortex Microcontroller Software Interface Standard) - ARM - - http://www.keil.com/pack/ - - - - CMSIS-Core(M): 5.3.0 (see revision history for details) - - Added provisions for compiler-independent C startup code. - CMSIS-Core(A): 1.1.4 (see revision history for details) - - Fixed __FPU_Enable. - CMSIS-DSP: 1.7.0 (see revision history for details) - - New Neon versions of f32 functions - - Python wrapper - - Preliminary cmake build - - Compilation flags for FFTs - - Changes to arm_math.h - CMSIS-NN: 1.2.0 (see revision history for details) - - New function for depthwise convolution with asymmetric quantization. - - New support functions for requantization. - CMSIS-RTOS: - - RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+) - CMSIS-RTOS2: - - RTX 5.5.1 (see revision history for details) - CMSIS-Driver: 2.7.1 - - WiFi Interface API 1.0.0 - Devices: - - Generalized C startup code for all Cortex-M familiy devices. - - Updated Cortex-A default memory regions and MMU configurations - - Moved Cortex-A memory and system config files to avoid include path issues - - - The following folders are deprecated - - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) - - CMSIS-Core(M): 5.2.1 (see revision history for details) - - Fixed compilation issue in cmsis_armclang_ltm.h - - - The following folders have been removed: - - CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/) - - CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/) - The following folders are deprecated - - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) - - CMSIS-Core(M): 5.2.0 (see revision history for details) - - Reworked Stack/Heap configuration for ARM startup files. - - Added Cortex-M35P device support. - - Added generic Armv8.1-M Mainline device support. - CMSIS-Core(A): 1.1.3 (see revision history for details) - CMSIS-DSP: 1.6.0 (see revision history for details) - - reworked DSP library source files - - reworked DSP library documentation - - Changed DSP folder structure - - moved DSP libraries to folder ./DSP/Lib - - ARM DSP Libraries are built with ARMCLANG - - Added DSP Libraries Source variant - CMSIS-RTOS2: - - RTX 5.5.0 (see revision history for details) - CMSIS-Driver: 2.7.0 - - Added WiFi Interface API 1.0.0-beta - - Added components for project specific driver implementations - CMSIS-Pack: 1.6.0 (see revision history for details) - Devices: - - Added Cortex-M35P and ARMv81MML device templates. - - Fixed C-Startup Code for GCC (aligned with other compilers) - Utilities: - - SVDConv 3.3.25 - - PackChk 1.3.82 - - - Aligned pack structure with repository. - The following folders are deprecated: - - CMSIS/Include/ - - CMSIS/DSP_Lib/ - - CMSIS-Core(M): 5.1.2 (see revision history for details) - - Added Cortex-M1 support (beta). - CMSIS-Core(A): 1.1.2 (see revision history for details) - CMSIS-NN: 1.1.0 - - Added new math functions. - CMSIS-RTOS2: - - API 2.1.3 (see revision history for details) - - RTX 5.4.0 (see revision history for details) - * Updated exception handling on Cortex-A - CMSIS-Driver: - - Flash Driver API V2.2.0 - Utilities: - - SVDConv 3.3.21 - - PackChk 1.3.71 - - - Updated Arm company brand. - CMSIS-Core(M): 5.1.1 (see revision history for details) - CMSIS-Core(A): 1.1.1 (see revision history for details) - CMSIS-DAP: 2.0.0 (see revision history for details) - CMSIS-NN: 1.0.0 - - Initial contribution of the bare metal Neural Network Library. - CMSIS-RTOS2: - - RTX 5.3.0 (see revision history for details) - - OS Tick API 1.0.1 - - - CMSIS-Core(M): 5.1.0 (see revision history for details) - - Added MPU Functions for ARMv8-M for Cortex-M23/M33. - - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler. - CMSIS-Core(A): 1.1.0 (see revision history for details) - - Added compiler_iccarm.h. - - Added additional access functions for physical timer. - CMSIS-DAP: 1.2.0 (see revision history for details) - CMSIS-DSP: 1.5.2 (see revision history for details) - CMSIS-Driver: 2.6.0 (see revision history for details) - - CAN Driver API V1.2.0 - - NAND Driver API V2.3.0 - CMSIS-RTOS: - - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata. - CMSIS-RTOS2: - - API 2.1.2 (see revision history for details) - - RTX 5.2.3 (see revision history for details) - Devices: - - Added GCC startup and linker script for Cortex-A9. - - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU. - - Added IAR startup code for Cortex-A9 - - - CMSIS-RTOS2: - - RTX 5.2.1 (see revision history for details) - - - CMSIS-Core(M): 5.0.2 (see revision history for details) - - Changed Version Control macros to be core agnostic. - - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7. - CMSIS-Core(A): 1.0.0 (see revision history for details) - - Initial release - - IRQ Controller API 1.0.0 - CMSIS-Driver: 2.05 (see revision history for details) - - All typedefs related to status have been made volatile. - CMSIS-RTOS2: - - API 2.1.1 (see revision history for details) - - RTX 5.2.0 (see revision history for details) - - OS Tick API 1.0.0 - CMSIS-DSP: 1.5.2 (see revision history for details) - - Fixed GNU Compiler specific diagnostics. - CMSIS-Pack: 1.5.0 (see revision history for details) - - added System Description File (*.SDF) Format - CMSIS-Zone: 0.0.1 (Preview) - - Initial specification draft - - - Package Description: - - added taxonomy for Cclass RTOS - CMSIS-RTOS2: - - API 2.1 (see revision history for details) - - RTX 5.1.0 (see revision history for details) - CMSIS-Core: 5.0.1 (see revision history for details) - - Added __PACKED_STRUCT macro - - Added uVisior support - - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__ - - Updated template for secure main function (main_s.c) - - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c) - CMSIS-DSP: 1.5.1 (see revision history for details) - - added ARMv8M DSP libraries. - CMSIS-Pack:1.4.9 (see revision history for details) - - added Pack Index File specification and schema file - - - Changed open source license to Apache 2.0 - CMSIS_Core: - - Added support for Cortex-M23 and Cortex-M33. - - Added ARMv8-M device configurations for mainline and baseline. - - Added CMSE support and thread context management for TrustZone for ARMv8-M - - Added cmsis_compiler.h to unify compiler behaviour. - - Updated function SCB_EnableICache (for Cortex-M7). - - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType - CMSIS-RTOS: - - bug fix in RTX 4.82 (see revision history for details) - CMSIS-RTOS2: - - new API including compatibility layer to CMSIS-RTOS - - reference implementation based on RTX5 - - supports all Cortex-M variants including TrustZone for ARMv8-M - CMSIS-SVD: - - reworked SVD format documentation - - removed SVD file database documentation as SVD files are distributed in packs - - updated SVDConv for Win32 and Linux - CMSIS-DSP: - - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. - - Added DSP libraries build projects to CMSIS pack. - - - - CMSIS-Core 4.30.0 (see revision history for details) - - CMSIS-DAP 1.1.0 (unchanged) - - CMSIS-Driver 2.04.0 (see revision history for details) - - CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details) - - CMSIS-Pack 1.4.1 (see revision history for details) - - CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details) - - CMSIS-SVD 1.3.1 (see revision history for details) - - - - CMSIS-Core 4.20 (see revision history for details) - - CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details) - - CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style) - - CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API) - - CMSIS-RTOS - -- API 1.02 (unchanged) - -- RTX 4.79 (see revision history for details) - - CMSIS-SVD 1.3.0 (see revision history for details) - - CMSIS-DAP 1.1.0 (extended with SWO support) - - - - CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions) - - CMSIS-DSP 1.4.5 (see revision history for details) - - CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API) - - CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions) - - CMSIS-RTOS - -- API 1.02 (unchanged) - -- RTX 4.78 (see revision history for details) - - CMSIS-SVD 1.2 (unchanged) - - - Adding Cortex-M7 support - - CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files) - - CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues) - - CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial) - - CMSIS-SVD 1.2 (Cortex-M7 extensions) - - CMSIS-RTOS RTX 4.75 (see revision history for details) - - - - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices - - - - CMSIS-Driver 2.02 (incompatible update) - - CMSIS-Pack 1.3 (see revision history for details) - - CMSIS-DSP 1.4.2 (unchanged) - - CMSIS-Core 3.30 (unchanged) - - CMSIS-RTOS RTX 4.74 (unchanged) - - CMSIS-RTOS API 1.02 (unchanged) - - CMSIS-SVD 1.10 (unchanged) - PACK: - - removed G++ specific files from PACK - - added Component Startup variant "C Startup" - - added Pack Checking Utility - - updated conditions to reflect tool-chain dependency - - added Taxonomy for Graphics - - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers" - - - - - CMSIS-RTOS 4.74 (see revision history for details) - - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1. - - - - - - - - - Software components for audio processing - Generic Interfaces for Evaluation and Development Boards - Drivers that support an external component available on an evaluation board - Compiler Software Extensions - Cortex Microcontroller Software Interface Components - Unified Device Drivers compliant to CMSIS-Driver Specifications - Startup, System Setup - Data exchange or data formatter - Drivers that support an extension board or shield - File Drive Support and File System - IoT cloud client connector - IoT specific software utility - Graphical User Interface - Network Stack using Internet Protocols - Real-time Operating System - Encryption for secure communication or storage - Universal Serial Bus Stack - Generic software utility components - - - - - - - -The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: -- simple, easy-to-use programmers model -- highly efficient ultra-low power operation -- excellent code density -- deterministic, high-performance interrupt handling -- upward compatibility with the rest of the Cortex-M processor family. - - - - - - - - - - - - - - - - -The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: -- simple, easy-to-use programmers model -- highly efficient ultra-low power operation -- excellent code density -- deterministic, high-performance interrupt handling -- upward compatibility with the rest of the Cortex-M processor family. - - - - - - - - - - - - - - - - - - - - - -The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA. -The ARM Cortex-M1 processor implements the ARMv6-M architecture profile. - - - - - - - - - - - - - - - - -The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: -- simple, easy-to-use programmers model -- highly efficient ultra-low power operation -- excellent code density -- deterministic, high-performance interrupt handling -- upward compatibility with the rest of the Cortex-M processor family. - - - - - - - - - - - - - - - - -The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: -- simple, easy-to-use programmers model -- highly efficient ultra-low power operation -- excellent code density -- deterministic, high-performance interrupt handling -- upward compatibility with the rest of the Cortex-M processor family. - - - - - - - - - - - - - - - - - - - - - -The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: -- simple, easy-to-use programmers model -- highly efficient ultra-low power operation -- excellent code density -- deterministic, high-performance interrupt handling -- upward compatibility with the rest of the Cortex-M processor family. - - - - - - - - - - - - - - - - - - - - - - - - - - -The Arm Cortex-M23 is based on the Armv8-M baseline architecture. -It is the smallest and most energy efficient Arm processor with Arm TrustZone technology. -Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security. - - - - - - - - - - - - - - - - - - - - - - - -The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller -class processor based on the Armv8-M mainline architecture with Arm TrustZone security. - - - - - - - - - - - - no DSP Instructions, no Floating Point Unit, no TrustZone - - - - - - - - no DSP Instructions, no Floating Point Unit, TrustZone - - - - - - - - DSP Instructions, Single Precision Floating Point Unit, no TrustZone - - - - - - - - DSP Instructions, Single Precision Floating Point Unit, TrustZone - - - - - - - - - -The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller -class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications. - - - - - - - - - - - - - no DSP Instructions, no Floating Point Unit, no TrustZone - - - - - - - - no DSP Instructions, no Floating Point Unit, TrustZone - - - - - - - - DSP Instructions, Single Precision Floating Point Unit, no TrustZone - - - - - - - - DSP Instructions, Single Precision Floating Point Unit, TrustZone - - - - - - - - -The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: -- simple, easy-to-use programmers model -- highly efficient ultra-low power operation -- excellent code density -- deterministic, high-performance interrupt handling - - - - - - - - - - - - - - - -The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: -- simple, easy-to-use programmers model -- highly efficient ultra-low power operation -- excellent code density -- deterministic, high-performance interrupt handling - - - - - - - - - - - - - - - - -Armv8-M Baseline based device with TrustZone - - - - - - - - - - - - - - - - - - -Armv8-M Mainline based device with TrustZone - - - - - - - - - - - - no DSP Instructions, no Floating Point Unit, TrustZone - - - - - - - - DSP Instructions, no Floating Point Unit, TrustZone - - - - - - - - no DSP Instructions, Single Precision Floating Point Unit, TrustZone - - - - - - - - DSP Instructions, Single Precision Floating Point Unit, TrustZone - - - - - - - - no DSP Instructions, Double Precision Floating Point Unit, TrustZone - - - - - - - - DSP Instructions, Double Precision Floating Point Unit, TrustZone - - - - - - - - - -Armv8.1-M Mainline based device with TrustZone and MVE - - - - - - - - - - - - - Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone - - - - - - - - - -The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full -virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit -Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family. - - - - - - - - - - - - - - - - - -The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture. -The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem, -an optional integrated GIC, and an optional L2 cache controller. - - - - - - - - - - - - - - - - - -The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. -The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, -and 8-bit Java bytecodes in Jazelle state. - - - - - - - - - - - - - - - - - - - Device interrupt controller interface - - - - - - RTOS Kernel system tick timer interface - - - - - - - CMSIS-RTOS API for Cortex-M, SC000, and SC300 - - - - - - CMSIS-RTOS API for Cortex-M, SC000, and SC300 - - - - - - - - USART Driver API for Cortex-M - - - - - - - SPI Driver API for Cortex-M - - - - - - - SAI Driver API for Cortex-M - - - - - - - I2C Driver API for Cortex-M - - - - - - - CAN Driver API for Cortex-M - - - - - - - Flash Driver API for Cortex-M - - - - - - - MCI Driver API for Cortex-M - - - - - - - NAND Flash Driver API for Cortex-M - - - - - - - Ethernet MAC and PHY Driver API for Cortex-M - - - - - - - - Ethernet MAC Driver API for Cortex-M - - - - - - - Ethernet PHY Driver API for Cortex-M - - - - - - - USB Device Driver API for Cortex-M - - - - - - - USB Host Driver API for Cortex-M - - - - - - - WiFi driver - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Armv6-M architecture based device - - - - - - - Armv7-M architecture based device - - - - - - - Armv8-M architecture based device - - - - - - - - - Armv8-M architecture based device with TrustZone - - - - - Armv6_7-M architecture based device - - - - - Armv6_7_8-M architecture based device - - - - - - Armv7-A architecture based device - - - - - - - - Cortex-M0 or Cortex-M0+ or SC000 processor based device - - - - - - Cortex-M1 - - - - Cortex-M3 or SC300 processor based device - - - - - Cortex-M4 processor based device - - - - Cortex-M4 processor based device using Floating Point Unit - - - - - - Cortex-M7 processor based device - - - - Cortex-M7 processor based device using Floating Point Unit - - - - - Cortex-M7 processor based device using Floating Point Unit (SP) - - - - Cortex-M7 processor based device using Floating Point Unit (DP) - - - - Cortex-M23 processor based device - - - - Cortex-M33 processor based device - - - - Cortex-M33 processor based device using Floating Point Unit - - - - Cortex-M35P processor based device - - - - Cortex-M35P processor based device using Floating Point Unit - - - - Armv8-M Baseline processor based device - - - - Armv8-M Mainline processor based device - - - - Armv8-M Mainline processor based device using Floating Point Unit - - - - - - CM33, no DSP, no FPU - - - - CM33, DSP, no FPU - - - - CM33, no DSP, SP FPU - - - - CM33, DSP, SP FPU - - - - - CM35P, no DSP, no FPU - - - - CM35P, DSP, no FPU - - - - CM35P, no DSP, SP FPU - - - - CM35P, DSP, SP FPU - - - - - Armv8-M Mainline, no DSP, no FPU - - - - Armv8-M Mainline, DSP, no FPU - - - - Armv8-M Mainline, no DSP, SP FPU - - - - Armv8-M Mainline, DSP, SP FPU - - - - - Cortex-A5 or Cortex-A9 processor based device - - - - - - Cortex-A7 processor based device - - - - - - Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5 - - - - - Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6 - - - - - - Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler - - - - - Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler - - - - - Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler - - - - - - Cortex-M1 based device for the Arm Compiler - - - - - Cortex-M1 based device in little endian mode for the Arm Compiler - - - - - Cortex-M1 based device in big endian mode for the Arm Compiler - - - - - - Cortex-M3 or SC300 processor based device for the Arm Compiler - - - - - Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler - - - - - Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler - - - - - - Cortex-M4 processor based device for the Arm Compiler - - - - - Cortex-M4 processor based device in little endian mode for the Arm Compiler - - - - - Cortex-M4 processor based device in big endian mode for the Arm Compiler - - - - - - Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler - - - - - Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler - - - - - Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler - - - - - - Cortex-M7 processor based device for the Arm Compiler - - - - - Cortex-M7 processor based device in little endian mode for the Arm Compiler - - - - - Cortex-M7 processor based device in big endian mode for the Arm Compiler - - - - - - Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler - - - - - - Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler - - - - - - Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler - - - - - - Cortex-M23 processor based device for the Arm Compiler - - - - - Cortex-M23 processor based device in little endian mode for the Arm Compiler - - - - - - Cortex-M33 processor based device for the Arm Compiler - - - - - Cortex-M33 processor based device in little endian mode for the Arm Compiler - - - - - - Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler - - - - - Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler - - - - - - Cortex-M33 processor, no DSP, no FPU, Arm Compiler - - - - - Cortex-M33 processor, DSP, no FPU, Arm Compiler - - - - - Cortex-M33 processor, no DSP, SP FPU, Arm Compiler - - - - - Cortex-M33 processor, DSP, SP FPU, Arm Compiler - - - - - Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler - - - - - Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler - - - - - Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler - - - - - Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler - - - - - - Cortex-M35P processor based device for the Arm Compiler - - - - - Cortex-M35P processor based device in little endian mode for the Arm Compiler - - - - - - Cortex-M35P processor based device using Floating Point Unit for the Arm Compiler - - - - - Cortex-M35P processor based device using Floating Point Unit in little endian mode for the Arm Compiler - - - - - - Cortex-M35P processor, no DSP, no FPU, Arm Compiler - - - - - Cortex-M35P processor, DSP, no FPU, Arm Compiler - - - - - Cortex-M35P processor, no DSP, SP FPU, Arm Compiler - - - - - Cortex-M35P processor, DSP, SP FPU, Arm Compiler - - - - - Cortex-M35P processor, little endian, no DSP, no FPU, Arm Compiler - - - - - Cortex-M35P processor, little endian, DSP, no FPU, Arm Compiler - - - - - Cortex-M35P processor, little endian, no DSP, SP FPU, Arm Compiler - - - - - Cortex-M35P processor, little endian, DSP, SP FPU, Arm Compiler - - - - - - Armv8-M Baseline processor based device for the Arm Compiler - - - - - Armv8-M Baseline processor based device in little endian mode for the Arm Compiler - - - - - - Armv8-M Mainline processor based device for the Arm Compiler - - - - - Armv8-M Mainline processor based device in little endian mode for the Arm Compiler - - - - - - Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler - - - - - Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler - - - - - - Armv8-M Mainline, no DSP, no FPU, Arm Compiler - - - - - Armv8-M Mainline, DSP, no FPU, Arm Compiler - - - - - Armv8-M Mainline, no DSP, SP FPU, Arm Compiler - - - - - Armv8-M Mainline, DSP, SP FPU, Arm Compiler - - - - - Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler - - - - - Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler - - - - - Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler - - - - - Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler - - - - - - - Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler - - - - - - Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler - - - - - Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler - - - - - Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler - - - - - - Cortex-M1 based device for the GCC Compiler - - - - - Cortex-M1 based device in little endian mode for the GCC Compiler - - - - - Cortex-M1 based device in big endian mode for the GCC Compiler - - - - - - Cortex-M3 or SC300 processor based device for the GCC Compiler - - - - - Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler - - - - - Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler - - - - - - Cortex-M4 processor based device for the GCC Compiler - - - - - Cortex-M4 processor based device in little endian mode for the GCC Compiler - - - - - Cortex-M4 processor based device in big endian mode for the GCC Compiler - - - - - - Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler - - - - - Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler - - - - - Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler - - - - - - Cortex-M7 processor based device for the GCC Compiler - - - - - Cortex-M7 processor based device in little endian mode for the GCC Compiler - - - - - Cortex-M7 processor based device in big endian mode for the GCC Compiler - - - - - - Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler - - - - - - Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler - - - - - - Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler - - - - - - Cortex-M23 processor based device for the GCC Compiler - - - - - Cortex-M23 processor based device in little endian mode for the GCC Compiler - - - - - - Cortex-M33 processor based device for the GCC Compiler - - - - - Cortex-M33 processor based device in little endian mode for the GCC Compiler - - - - - - Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler - - - - - Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler - - - - - - CM33, no DSP, no FPU, GCC Compiler - - - - - CM33, DSP, no FPU, GCC Compiler - - - - - CM33, no DSP, SP FPU, GCC Compiler - - - - - CM33, DSP, SP FPU, GCC Compiler - - - - - CM33, little endian, no DSP, no FPU, GCC Compiler - - - - - CM33, little endian, DSP, no FPU, GCC Compiler - - - - - CM33, little endian, no DSP, SP FPU, GCC Compiler - - - - - CM33, little endian, DSP, SP FPU, GCC Compiler - - - - - - Cortex-M35P processor based device for the GCC Compiler - - - - - Cortex-M35P processor based device in little endian mode for the GCC Compiler - - - - - - Cortex-M35P processor based device using Floating Point Unit for the GCC Compiler - - - - - Cortex-M35P processor based device using Floating Point Unit in little endian mode for the GCC Compiler - - - - - - CM35P, no DSP, no FPU, GCC Compiler - - - - - CM35P, DSP, no FPU, GCC Compiler - - - - - CM35P, no DSP, SP FPU, GCC Compiler - - - - - CM35P, DSP, SP FPU, GCC Compiler - - - - - CM35P, little endian, no DSP, no FPU, GCC Compiler - - - - - CM35P, little endian, DSP, no FPU, GCC Compiler - - - - - CM35P, little endian, no DSP, SP FPU, GCC Compiler - - - - - CM35P, little endian, DSP, SP FPU, GCC Compiler - - - - - - Armv8-M Baseline processor based device for the GCC Compiler - - - - - Armv8-M Baseline processor based device in little endian mode for the GCC Compiler - - - - - - Armv8-M Mainline processor based device for the GCC Compiler - - - - - Armv8-M Mainline processor based device in little endian mode for the GCC Compiler - - - - - - Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler - - - - - Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler - - - - - - Armv8-M Mainline, no DSP, no FPU, GCC Compiler - - - - - Armv8-M Mainline, DSP, no FPU, GCC Compiler - - - - - Armv8-M Mainline, no DSP, SP FPU, GCC Compiler - - - - - Armv8-M Mainline, DSP, SP FPU, GCC Compiler - - - - - Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler - - - - - Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler - - - - - Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler - - - - - Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler - - - - - - - Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler - - - - - - Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler - - - - - Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler - - - - - Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler - - - - - - Cortex-M1 based device for the IAR Compiler - - - - - Cortex-M1 based device in little endian mode for the IAR Compiler - - - - - Cortex-M1 based device in big endian mode for the IAR Compiler - - - - - - Cortex-M3 or SC300 processor based device for the IAR Compiler - - - - - Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler - - - - - Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler - - - - - - Cortex-M4 processor based device for the IAR Compiler - - - - - Cortex-M4 processor based device in little endian mode for the IAR Compiler - - - - - Cortex-M4 processor based device in big endian mode for the IAR Compiler - - - - - - Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler - - - - - Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler - - - - - Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler - - - - - - Cortex-M7 processor based device for the IAR Compiler - - - - - Cortex-M7 processor based device in little endian mode for the IAR Compiler - - - - - Cortex-M7 processor based device in big endian mode for the IAR Compiler - - - - - - Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler - - - - - - Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler - - - - - - Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler - - - - - Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler - - - - - - Cortex-M23 processor based device for the IAR Compiler - - - - - Cortex-M23 processor based device in little endian mode for the IAR Compiler - - - - - - Cortex-M33 processor based device for the IAR Compiler - - - - - Cortex-M33 processor based device in little endian mode for the IAR Compiler - - - - - - Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler - - - - - Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler - - - - - - CM33, no DSP, no FPU, IAR Compiler - - - - - CM33, DSP, no FPU, IAR Compiler - - - - - CM33, no DSP, SP FPU, IAR Compiler - - - - - CM33, DSP, SP FPU, IAR Compiler - - - - - CM33, little endian, no DSP, no FPU, IAR Compiler - - - - - CM33, little endian, DSP, no FPU, IAR Compiler - - - - - CM33, little endian, no DSP, SP FPU, IAR Compiler - - - - - CM33, little endian, DSP, SP FPU, IAR Compiler - - - - - - Cortex-M35P processor based device for the IAR Compiler - - - - - Cortex-M35P processor based device in little endian mode for the IAR Compiler - - - - - - Cortex-M35P processor based device using Floating Point Unit for the IAR Compiler - - - - - Cortex-M35P processor based device using Floating Point Unit in little endian mode for the IAR Compiler - - - - - - CM35P, no DSP, no FPU, IAR Compiler - - - - - CM35P, DSP, no FPU, IAR Compiler - - - - - CM35P, no DSP, SP FPU, IAR Compiler - - - - - CM35P, DSP, SP FPU, IAR Compiler - - - - - CM35P, little endian, no DSP, no FPU, IAR Compiler - - - - - CM35P, little endian, DSP, no FPU, IAR Compiler - - - - - CM35P, little endian, no DSP, SP FPU, IAR Compiler - - - - - CM35P, little endian, DSP, SP FPU, IAR Compiler - - - - - - Armv8-M Baseline processor based device for the IAR Compiler - - - - - Armv8-M Baseline processor based device in little endian mode for the IAR Compiler - - - - - - Armv8-M Mainline processor based device for the IAR Compiler - - - - - Armv8-M Mainline processor based device in little endian mode for the IAR Compiler - - - - - - Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler - - - - - Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler - - - - - - Armv8-M Mainline, no DSP, no FPU, IAR Compiler - - - - - Armv8-M Mainline, DSP, no FPU, IAR Compiler - - - - - Armv8-M Mainline, no DSP, SP FPU, IAR Compiler - - - - - Armv8-M Mainline, DSP, SP FPU, IAR Compiler - - - - - Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler - - - - - Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler - - - - - Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler - - - - - Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler - - - - - - - Generic Arm Cortex-M0 device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-M0+ device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-M1 device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-M3 device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-M4 device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-M7 device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-M23 device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-M33 device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-M35P device startup and depends on CMSIS Core - - - - - - Generic Arm SC000 device startup and depends on CMSIS Core - - - - - - Generic Arm SC300 device startup and depends on CMSIS Core - - - - - - Generic Armv8-M Baseline device startup and depends on CMSIS Core - - - - - - Generic Armv8-M Mainline device startup and depends on CMSIS Core - - - - - - Generic Armv8.1-M Mainline device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-A5 device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-A7 device startup and depends on CMSIS Core - - - - - - Generic Arm Cortex-A9 device startup and depends on CMSIS Core - - - - - - - Components required for DSP - - - - - - - - Components required for NN - - - - - - Components required for RTOS RTX - - - - - - - Components required for RTOS RTX IFX - - - - - - - - Components required for RTOS RTX5 - - - - - - Components required for RTOS2 RTX5 - - - - - - - Components required for RTOS2 RTX5 on Armv7-A - - - - - - - - - Components required for RTOS2 RTX5 Library - - - - - - - Components required for RTOS2 RTX5 in Non-Secure Domain - - - - - - - - - Components required for OS Tick Private Timer - - - - - - Components required for OS Tick Generic Physical Timer - - - - - - - - - - CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M - - - - - - - - - - - - - CMSIS-CORE for Cortex-A - - - - - - - - - - - System and Startup for Generic Arm Cortex-M0 device - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm Cortex-M0 device - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-M0+ device - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-M1 device - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm Cortex-M1 device - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-M3 device - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm Cortex-M3 device - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-M4 device - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm Cortex-M4 device - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-M7 device - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm Cortex-M7 device - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-M23 device - - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm Cortex-M23 device - - - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-M33 device - - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm Cortex-M33 device - - - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-M35P device - - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm Cortex-M35P device - - - - - - - - - - - - - - - - - System and Startup for Generic Arm SC000 device - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm SC000 device - - - - - - - - - - - - - - - System and Startup for Generic Arm SC300 device - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Arm SC300 device - - - - - - - - - - - - - - - System and Startup for Generic Armv8-M Baseline device - - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Armv8-M Baseline device - - - - - - - - - - - - - - - - System and Startup for Generic Armv8-M Mainline device - - - - - - - - - - - - - - DEPRECATED: System and Startup for Generic Armv8-M Mainline device - - - - - - - - - - - - - - - - System and Startup for Generic Armv8.1-M Mainline device - - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-A5 device - - - - - - - - - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-A7 device - - - - - - - - - - - - - - - - - - - - - - System and Startup for Generic Arm Cortex-A9 device - - - - - - - - - - - - - - - - - - - - - - IRQ Controller implementation using GIC - - - - - - - - OS Tick implementation using Private Timer - - - - - - - OS Tick implementation using Generic Physical Timer - - - - - - - - CMSIS-DSP Library for Cortex-M, SC000, and SC300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CMSIS-DSP Library for Cortex-M, SC000, and SC300 - - - - - - - - - - - - - - - - - - - - - - - CMSIS-NN Neural Network Library - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300 - - - #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ - #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata - - - #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ - #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300 - - - #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ - #define RTE_CMSIS_RTOS_RTX5 /* CMSIS-RTOS Keil RTX5 */ - - - - - - - - - - - - CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library) - - - #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ - #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library) - - - #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ - #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ - #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source) - - - #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ - #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ - #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CMSIS-RTOS2 RTX5 for Armv7-A (Source) - - - #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ - #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ - #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source) - - - #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ - #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ - #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ - #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Access to #include Driver_USART.h file and code template for custom implementation - - - - - - - Access to #include Driver_SPI.h file and code template for custom implementation - - - - - - - Access to #include Driver_SAI.h file and code template for custom implementation - - - - - - - Access to #include Driver_I2C.h file and code template for custom implementation - - - - - - - Access to #include Driver_CAN.h file and code template for custom implementation - - - - - - - Access to #include Driver_Flash.h file and code template for custom implementation - - - - - - - Access to #include Driver_MCI.h file and code template for custom implementation - - - - - - - Access to #include Driver_NAND.h file and code template for custom implementation - - - - - - - Access to #include Driver_ETH_PHY/MAC.h files and code templates for custom implementation - - - - - - - - - Access to #include Driver_ETH_MAC.h file and code template for custom implementation - - - - - - - Access to #include Driver_ETH_PHY.h file and code template for custom implementation - - - - - - - Access to #include Driver_USBD.h file and code template for custom implementation - - - - - - - Access to #include Driver_USBH.h file and code template for custom implementation - - - - - - - Access to #include Driver_WiFi.h file - - - - - - - - - - uVision Simulator - - - - - - - - - - - - - - - - - - - - - - - - - - - - EWARM Simulator - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DSP_Lib Class Marks example - - - - - - - - - Getting Started - - - - - DSP_Lib Convolution example - - - - - - - - - Getting Started - - - - - DSP_Lib Dotproduct example - - - - - - - - - Getting Started - - - - - DSP_Lib FFT Bin example - - - - - - - - - Getting Started - - - - - DSP_Lib FIR example - - - - - - - - - Getting Started - - - - - DSP_Lib Graphic Equalizer example - - - - - - - - - Getting Started - - - - - DSP_Lib Linear Interpolation example - - - - - - - - - Getting Started - - - - - DSP_Lib Matrix example - - - - - - - - - Getting Started - - - - - DSP_Lib Signal Convergence example - - - - - - - - - Getting Started - - - - - DSP_Lib Sinus/Cosinus example - - - - - - - - - Getting Started - - - - - DSP_Lib Variance example - - - - - - - - - Getting Started - - - - - Neural Network CIFAR10 example - - - - - - - - - - Getting Started - - - - - Neural Network CIFAR10 example - - - - - - - - - - Getting Started - - - - - Neural Network GRU example - - - - - - - - - - Getting Started - - - - - Neural Network GRU example - - - - - - - - - - Getting Started - - - - - CMSIS-RTOS2 Blinky example - - - - - - - - - Getting Started - - - - - CMSIS-RTOS2 mixed API v1 and v2 - - - - - - - - - Getting Started - - - - - CMSIS-RTOS2 Message Queue Example - - - - - - - - - - Getting Started - - - - - CMSIS-RTOS2 Memory Pool Example - - - - - - - - - - Getting Started - - - - - Bare-metal secure/non-secure example without RTOS - - - - - - - - - Getting Started - - - - - Secure/non-secure RTOS example with thread context management - - - - - - - - - Getting Started - - - - - Secure/non-secure RTOS example with security test cases and system recovery - - - - - - - - - Getting Started - - - - - - diff --git a/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/manifest b/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/manifest deleted file mode 100644 index 38b424c762aa..000000000000 --- a/drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/manifest +++ /dev/null @@ -1,50 +0,0 @@ -pdsc: ARM.CMSIS.pdsc -preproc: - - clean: CMSIS/Documentation/(Core,Core_A,DAP,Driver,DSP,NN,General,Pack,RTOS,RTOS2,SVD,Zone) - - doxygen: CMSIS/DoxyGen/Core/core.dxy - - doxygen: CMSIS/DoxyGen/Core_A/core_A.dxy - - doxygen: CMSIS/DoxyGen/DAP/dap.dxy - - doxygen: CMSIS/DoxyGen/Driver/Driver.dxy - - doxygen: CMSIS/DoxyGen/DSP/dsp.dxy - - doxygen: CMSIS/DoxyGen/General/general.dxy - - doxygen: CMSIS/DoxyGen/NN/nn.dxy - - doxygen: CMSIS/DoxyGen/Pack/Pack.dxy - - doxygen: CMSIS/DoxyGen/RTOS/rtos.dxy - - doxygen: CMSIS/DoxyGen/RTOS2/rtos.dxy - - doxygen: CMSIS/DoxyGen/SVD/svd.dxy - - doxygen: CMSIS/DoxyGen/Zone/zone.dxy -glob: - - LICENSE.txt - - Device/**/* - - CMSIS/Core/Include/**/* - - CMSIS/Core/Include/**/*: CMSIS/Include/ - - CMSIS/Core/Template/**/* - - CMSIS/Core_A/**/* - - CMSIS/DAP/**/* - - CMSIS/Driver/**/* - - CMSIS/DSP/Include/**/* - - CMSIS/DSP/Source/**/* - - CMSIS/DSP/Projects/**/* - - CMSIS/DSP/Examples/**/* - - CMSIS/DSP/Include/**/*: CMSIS/Include/ - - CMSIS/DSP/Lib/**/* - - CMSIS/NN/**/* - - CMSIS/Pack/**/* - - CMSIS/RTOS/**/* - - CMSIS/RTOS2/**/* - - CMSIS/Utilities/ARM_Example.*: CMSIS/SVD/ARM_Example. - - CMSIS/Utilities/CMSIS-SVD.xsd - - CMSIS/Utilities/PACK.xsd - - CMSIS/Utilities/PackIndex.xsd - - CMSIS/Utilities/Win32/**/* - - CMSIS/Utilities/Linux-gcc-4.4.4/**/* - - CMSIS/Utilities/Linux-gcc-4.8.3/**/* - - CMSIS/Documentation/**/* - - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/Core/html/search/search.css - - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/Core_A/html/search/search.css - - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/Driver/html/search/search.css - - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/Pack/html/search/search.css - - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/DSP/html/search/search.css - - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/DAP/html/search/search.css - - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/NN/html/search/search.css - - CMSIS/DoxyGen/Zone/genmodel/**/*: CMSIS/Documentation/Zone/genmodel/ diff --git a/drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.c b/drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.c index 226041aac786..aa29e13ac807 100644 --- a/drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.c +++ b/drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.c @@ -23,6 +23,9 @@ // #define pr_fmt(fmt) "bos0614: %s: " fmt, __func__ +#define DEBUG +//#undef DEBUG + #include #include @@ -31,8 +34,15 @@ #include "bsp/boards/boreasTime.h" #include "bsp/drivers/i2c/i2c.h" -#include "bsp/drivers/haptic/bos0614Driver.h" #include "bsp/drivers/haptic/bos0614Register.h" +#include "bsp/drivers/haptic/bos0614Driver.h" + +#ifdef DEBUG +#undef pr_debug +#define pr_debug pr_info +#undef dev_dbg +#define dev_dbg dev_info +#endif #define BOS0614_CHIP_ID (0x0D) #define BOS0614_I2C_ADDRESS (0x2c) @@ -182,6 +192,7 @@ static bool resetSoftware(Context *ctx) { bool res; + pr_debug("enter\n"); ctx->reg.CONFIG_0614.bit.RST = 0x1; res = writeReg(ctx, &ctx->reg.CONFIG_0614.reg); @@ -622,6 +633,8 @@ static bool validateIcWorking(Context *ctx) res = res && readRegister(ctx, &ctx->reg.CONFIG_0614.reg); res = res && ctx->reg.CONFIG_0614.bit.PLAY == bos0614SamplingRate_512Ksps; + pr_debug("ic is%s working!!!\n", res ? "" : " NOT"); + return res; } @@ -1780,78 +1793,85 @@ static BOS0614_REGS bOS0614Regs = .REG47_0614.reg.generic.addr = ADDRESS_BOS0614_REG47_REG, }; -static uint8_t regAddrToRead[] = {ADDRESS_BOS0614_REFERENCE_REG, - ADDRESS_BOS0614_IC_STATUS_REG, - ADDRESS_BOS0614_READ_REG, - ADDRESS_BOS0614_GPIOX_REG, - ADDRESS_BOS0614_TC_REG, - ADDRESS_BOS0614_CONFIG_REG, - ADDRESS_BOS0614_SENSECONFIG_REG, - ADDRESS_BOS0614_SENSE0_REG, - ADDRESS_BOS0614_SENSE0P_REG, - ADDRESS_BOS0614_SENSE0R_REG, - ADDRESS_BOS0614_SENSE0S_REG, - ADDRESS_BOS0614_SENSE1_REG, - ADDRESS_BOS0614_SENSE1P_REG, - ADDRESS_BOS0614_SENSE1R_REG, - ADDRESS_BOS0614_SENSE1S_REG, - ADDRESS_BOS0614_SENSE2_REG, - ADDRESS_BOS0614_SENSE2P_REG, - ADDRESS_BOS0614_SENSE2R_REG, - ADDRESS_BOS0614_SENSE2S_REG, - ADDRESS_BOS0614_SENSE3_REG, - ADDRESS_BOS0614_SENSE3P_REG, - ADDRESS_BOS0614_SENSE3R_REG, - ADDRESS_BOS0614_SENSE3S_REG, - ADDRESS_BOS0614_SENSESTATUS_REG, - ADDRESS_BOS0614_SENSEDATA0_REG, - ADDRESS_BOS0614_SENSEDATA1_REG, - ADDRESS_BOS0614_SENSEDATA2_REG, - ADDRESS_BOS0614_SENSEDATA3_REG, - ADDRESS_BOS0614_SENSERAW0_REG, - ADDRESS_BOS0614_SENSERAW1_REG, - ADDRESS_BOS0614_SENSERAW2_REG, - ADDRESS_BOS0614_SENSERAW3_REG, - ADDRESS_BOS0614_KPA_REG, - ADDRESS_BOS0614_KP_KI_REG, - ADDRESS_BOS0614_DEADTIME_REG, - ADDRESS_BOS0614_PARCAP_REG, - ADDRESS_BOS0614_SUP_RISE_REG, - ADDRESS_BOS0614_TRIM_REG, - ADDRESS_BOS0614_CHIP_ID_REG, - ADDRESS_BOS0614_VFEEDBACK_REG, - ADDRESS_BOS0614_FIFO_STATE_REG, - ADDRESS_BOS0614_AUTO_STATE_REG, - ADDRESS_BOS0614_BIST_REG, - ADDRESS_BOS0614_BISTRES_REG, - ADDRESS_BOS0614_DEBUG_REG, - ADDRESS_BOS0614_THRESH_REG, - ADDRESS_BOS0614_REG38_REG, - ADDRESS_BOS0614_REG39_REG, - ADDRESS_BOS0614_CALIB_DATA_REG, - ADDRESS_BOS0614_REG3B_REG, - ADDRESS_BOS0614_REG3C_REG, - ADDRESS_BOS0614_REG3D_REG, - ADDRESS_BOS0614_REG3E_REG, - ADDRESS_BOS0614_REG3F_REG, - ADDRESS_BOS0614_REG40_REG, - ADDRESS_BOS0614_REG41_REG, - ADDRESS_BOS0614_REG42_REG, - ADDRESS_BOS0614_REG43_REG, - ADDRESS_BOS0614_REG44_REG, - ADDRESS_BOS0614_REG45_REG, - ADDRESS_BOS0614_REG46_REG, - ADDRESS_BOS0614_REG47_REG}; +static Bos0614RegisterStruct regToRead[] = { + {.addr = ADDRESS_BOS0614_REFERENCE_REG,}, + {.addr = ADDRESS_BOS0614_IC_STATUS_REG,}, + {.addr = ADDRESS_BOS0614_READ_REG,}, + {.addr = ADDRESS_BOS0614_GPIOX_REG,}, + {.addr = ADDRESS_BOS0614_TC_REG,}, + {.addr = ADDRESS_BOS0614_CONFIG_REG,}, + {.addr = ADDRESS_BOS0614_SENSECONFIG_REG,}, + {.addr = ADDRESS_BOS0614_SENSE0_REG,}, + {.addr = ADDRESS_BOS0614_SENSE0P_REG,}, + {.addr = ADDRESS_BOS0614_SENSE0R_REG,}, + {.addr = ADDRESS_BOS0614_SENSE0S_REG,}, + {.addr = ADDRESS_BOS0614_SENSE1_REG,}, + {.addr = ADDRESS_BOS0614_SENSE1P_REG,}, + {.addr = ADDRESS_BOS0614_SENSE1R_REG,}, + {.addr = ADDRESS_BOS0614_SENSE1S_REG,}, + {.addr = ADDRESS_BOS0614_SENSE2_REG,}, + {.addr = ADDRESS_BOS0614_SENSE2P_REG,}, + {.addr = ADDRESS_BOS0614_SENSE2R_REG,}, + {.addr = ADDRESS_BOS0614_SENSE2S_REG,}, + {.addr = ADDRESS_BOS0614_SENSE3_REG,}, + {.addr = ADDRESS_BOS0614_SENSE3P_REG,}, + {.addr = ADDRESS_BOS0614_SENSE3R_REG,}, + {.addr = ADDRESS_BOS0614_SENSE3S_REG,}, + {.addr = ADDRESS_BOS0614_SENSESTATUS_REG,}, + {.addr = ADDRESS_BOS0614_SENSEDATA0_REG,}, + {.addr = ADDRESS_BOS0614_SENSEDATA1_REG,}, + {.addr = ADDRESS_BOS0614_SENSEDATA2_REG,}, + {.addr = ADDRESS_BOS0614_SENSEDATA3_REG,}, + {.addr = ADDRESS_BOS0614_SENSERAW0_REG,}, + {.addr = ADDRESS_BOS0614_SENSERAW1_REG,}, + {.addr = ADDRESS_BOS0614_SENSERAW2_REG,}, + {.addr = ADDRESS_BOS0614_SENSERAW3_REG,}, + {.addr = ADDRESS_BOS0614_KPA_REG,}, + {.addr = ADDRESS_BOS0614_KP_KI_REG,}, + {.addr = ADDRESS_BOS0614_DEADTIME_REG,}, + {.addr = ADDRESS_BOS0614_PARCAP_REG,}, + {.addr = ADDRESS_BOS0614_SUP_RISE_REG,}, + {.addr = ADDRESS_BOS0614_TRIM_REG,}, + {.addr = ADDRESS_BOS0614_CHIP_ID_REG,}, + {.addr = ADDRESS_BOS0614_VFEEDBACK_REG,}, + {.addr = ADDRESS_BOS0614_FIFO_STATE_REG,}, + {.addr = ADDRESS_BOS0614_AUTO_STATE_REG,}, + {.addr = ADDRESS_BOS0614_BIST_REG,}, + {.addr = ADDRESS_BOS0614_BISTRES_REG,}, + {.addr = ADDRESS_BOS0614_DEBUG_REG,}, + {.addr = ADDRESS_BOS0614_THRESH_REG,}, + {.addr = ADDRESS_BOS0614_REG38_REG,}, + {.addr = ADDRESS_BOS0614_REG39_REG,}, + {.addr = ADDRESS_BOS0614_CALIB_DATA_REG,}, + {.addr = ADDRESS_BOS0614_REG3B_REG,}, + {.addr = ADDRESS_BOS0614_REG3C_REG,}, + {.addr = ADDRESS_BOS0614_REG3D_REG,}, + {.addr = ADDRESS_BOS0614_REG3E_REG,}, + {.addr = ADDRESS_BOS0614_REG3F_REG,}, + {.addr = ADDRESS_BOS0614_REG40_REG,}, + {.addr = ADDRESS_BOS0614_REG41_REG,}, + {.addr = ADDRESS_BOS0614_REG42_REG,}, + {.addr = ADDRESS_BOS0614_REG43_REG,}, + {.addr = ADDRESS_BOS0614_REG44_REG,}, + {.addr = ADDRESS_BOS0614_REG45_REG,}, + {.addr = ADDRESS_BOS0614_REG46_REG,}, + {.addr = ADDRESS_BOS0614_REG47_REG,}, + }; + +Bos0614RegisterStruct *getAllRegsPtr(void) +{ + return regToRead; +} static bool readAllRegister(Context *ctx) { uint32_t index; bool res = true; - for (index = 0; index < DATA_ARRAY_LENGTH(regAddrToRead) && res; index++) + for (index = 0; index < DATA_ARRAY_LENGTH(regToRead) && res; index++) { uint16_t dummy; - res = bos0614GetRegister(&ctx->hDriver, regAddrToRead[index], &dummy); + res = bos0614GetRegister(&ctx->hDriver, regToRead[index].addr, &dummy); } return res; @@ -1861,10 +1881,22 @@ static bool setDefaultConfig(Context *ctx) { bool res = true; - //Reset configuration of the register; + pr_debug("enter\n"); + + //No need to copy registers again here!!! memcpy(&ctx->reg, &bOS0614Regs, sizeof(bOS0614Regs)); + //Why do we need to do a dummy read??? res = readAllRegister(ctx); + //bosDriverI2cProbe calls i2cBoreasLinuxInit + // i2cBoreasLinuxInit calls readDeviceTree + // readDeviceTree populates regToRead with default configuration + // + //Read SENSECONFIG to determine whether power cut occurred + //and necessary to apply default config provided in device tree + res = readRegister(ctx, &ctx->reg.SENSECONFIG_0614.reg); + res = res && ctx->reg.SENSECONFIG_0614.reg.generic.value == regToRead[ADDRESS_BOS0614_SENSECONFIG_REG].value; + ctx->reg.SENSECONFIG_0614.bit.CH0 = BOS0614_DISABLE; ctx->reg.SENSECONFIG_0614.bit.CH1 = BOS0614_DISABLE; ctx->reg.SENSECONFIG_0614.bit.CH2 = BOS0614_DISABLE; @@ -1875,12 +1907,21 @@ static bool setDefaultConfig(Context *ctx) ctx->reg.SENSECONFIG_0614.reg.generic.addr, ctx->reg.SENSECONFIG_0614.reg.generic.value); -// Bos0614Register *reg[] = {&ctx->reg.SENSECONFIG_0614.reg}; -// for (uint32_t index = 0; index < DATA_ARRAY_LENGTH(reg); index++) -// { -// res = res && ctx->hDriver.setRegister(&ctx->hDriver, reg[index]->generic.addr, -// reg[index]->generic.value); -// } + //This happens when SENSECONFIG register value from IC + //won't match config from device tree + if (res == false) + { + uint32_t index; + res = true; + for (index = 0; index < DATA_ARRAY_LENGTH(regToRead); index++) + { + if (regToRead[index].value != 0) + res = res && ctx->hDriver.setRegister(&ctx->hDriver, + regToRead[index].addr, + regToRead[index].value); + } + } + return res; } diff --git a/drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.h b/drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.h index ee5203df7d58..469dcd94ea45 100644 --- a/drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.h +++ b/drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.h @@ -45,5 +45,6 @@ HapticDriver *bos0614DriverI2cInit(Bos0614Resource resources); HapticDriver *bos0614DriverSpiInit(Spi *spi, Gpio *gpioA, Gpio *gpioD); +Bos0614RegisterStruct *getAllRegsPtr(void); #endif //DKCORE_BOS0614DRIVER_H