mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (370 commits) ARM: S3C2443: Add set_rate and round_rate calls for armdiv clock ARM: S3C2443: Remove #if 0 for clk_mpll ARM: S3C2443: Update notes on MPLLREF clock ARM: S3C2443: Further clksrc-clk conversions ARM: S3C2443: Change to using plat-samsung clksrc-clk implementation USB: Fix s3c-hsotg build following Samsung platform header moves ARM: S3C64XX: Reintroduce unconditional build of audio device ARM: 5961/1: ux500: fix CLKRST addresses ARM: 5977/1: arm: Enable backtrace printing on oops when PC is corrupted ASoC: Fix S3C64xx IIS driver for Samsung header reorg ARM: S3C2440: Fix plat-s3c24xx move of s3c2440/s3c2442 support [ARM] pxa: fix typo in mxm8x10.h [ARM] pxa/raumfeld: set GPIO drive bits for LED pins [ARM] pxa/zeus: Add support for mcp2515 CAN bus [ARM] pxa/zeus: Add support for onboard max6369 watchdog [ARM] pxa/zeus: Add Eurotech as the manufacturer [ARM] pxa/zeus: Correct the USB host initialisation flags [ARM] pxa/zeus: Allow usage of 8250-compatible UART in uncompress [ARM] pxa: refactor uncompress.h for non-PXA uarts [ARM] mmp2: fix incorrect calling of chip->mask_ack() for 2nd level cascaded IRQs ...
This commit is contained in:
Linus Torvalds
commit
dca1d9f6d7
627 changed files with 45021 additions and 9429 deletions
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@ -447,7 +447,7 @@ config SERIAL_CLPS711X_CONSOLE
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config SERIAL_SAMSUNG
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tristate "Samsung SoC serial support"
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depends on ARM && PLAT_S3C
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depends on ARM && PLAT_SAMSUNG
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select SERIAL_CORE
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help
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Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
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@ -455,11 +455,18 @@ config SERIAL_SAMSUNG
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provide all of these ports, depending on how the serial port
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pins are configured.
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config SERIAL_SAMSUNG_UARTS_4
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bool
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depends on ARM && PLAT_SAMSUNG
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default y if CPU_S3C2443
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help
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Internal node for the common case of 4 Samsung compatible UARTs
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config SERIAL_SAMSUNG_UARTS
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int
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depends on ARM && PLAT_S3C
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depends on ARM && PLAT_SAMSUNG
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default 2 if ARCH_S3C2400
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default 4 if ARCH_S5PC1XX || ARCH_S3C64XX || CPU_S3C2443
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default 4 if SERIAL_SAMSUNG_UARTS_4
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default 3
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help
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Select the number of available UART ports for the Samsung S3C
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@ -526,20 +533,30 @@ config SERIAL_S3C24A0
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Serial port support for the Samsung S3C24A0 SoC
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config SERIAL_S3C6400
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tristate "Samsung S3C6400/S3C6410 Serial port support"
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depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410)
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tristate "Samsung S3C6400/S3C6410/S5P6440 Seria port support"
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depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440)
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select SERIAL_SAMSUNG_UARTS_4
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default y
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help
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Serial port support for the Samsung S3C6400 and S3C6410
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Serial port support for the Samsung S3C6400, S3C6410 and S5P6440
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SoCs
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config SERIAL_S5PC100
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tristate "Samsung S5PC100 Serial port support"
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depends on SERIAL_SAMSUNG && CPU_S5PC100
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select SERIAL_SAMSUNG_UARTS_4
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default y
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help
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Serial port support for the Samsung S5PC100 SoCs
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config SERIAL_S5PV210
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tristate "Samsung S5PV210 Serial port support"
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depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442)
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select SERIAL_SAMSUNG_UARTS_4 if CPU_S5PV210
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default y
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help
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Serial port support for Samsung's S5P Family of SoC's
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config SERIAL_MAX3100
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tristate "MAX3100 support"
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depends on SPI
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@ -996,7 +1013,7 @@ config SERIAL_IP22_ZILOG_CONSOLE
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config SERIAL_SH_SCI
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tristate "SuperH SCI(F) serial port support"
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depends on HAVE_CLK && (SUPERH || H8300)
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depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE)
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select SERIAL_CORE
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config SERIAL_SH_SCI_NR_UARTS
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@ -45,6 +45,7 @@ obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
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obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
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obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
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obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o
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obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o
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obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
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obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
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obj-$(CONFIG_SERIAL_MUX) += mux.o
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@ -440,7 +440,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
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temp = readl(sport->port.membase + USR2);
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if (temp & USR2_BRCD) {
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writel(temp | USR2_BRCD, sport->port.membase + USR2);
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writel(USR2_BRCD, sport->port.membase + USR2);
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if (uart_handle_break(&sport->port))
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continue;
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}
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|
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@ -102,6 +102,7 @@ static struct s3c24xx_uart_info s3c2412_uart_inf = {
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.name = "Samsung S3C2412 UART",
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.type = PORT_S3C2412,
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.fifosize = 64,
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.has_divslot = 1,
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.rx_fifomask = S3C2440_UFSTAT_RXMASK,
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.rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
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.rx_fifofull = S3C2440_UFSTAT_RXFULL,
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154
drivers/serial/s5pv210.c
Normal file
154
drivers/serial/s5pv210.c
Normal file
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@ -0,0 +1,154 @@
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/* linux/drivers/serial/s5pv210.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* Based on drivers/serial/s3c6400.c
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*
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* Driver for Samsung S5PV210 SoC UARTs.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <plat/regs-serial.h>
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#include "samsung.h"
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static int s5pv210_serial_setsource(struct uart_port *port,
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struct s3c24xx_uart_clksrc *clk)
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{
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unsigned long ucon = rd_regl(port, S3C2410_UCON);
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if (strcmp(clk->name, "pclk") == 0)
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ucon &= ~S5PV210_UCON_CLKMASK;
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else if (strcmp(clk->name, "uclk1") == 0)
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ucon |= S5PV210_UCON_CLKMASK;
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else {
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printk(KERN_ERR "unknown clock source %s\n", clk->name);
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return -EINVAL;
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}
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wr_regl(port, S3C2410_UCON, ucon);
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return 0;
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}
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static int s5pv210_serial_getsource(struct uart_port *port,
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struct s3c24xx_uart_clksrc *clk)
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{
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u32 ucon = rd_regl(port, S3C2410_UCON);
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clk->divisor = 1;
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switch (ucon & S5PV210_UCON_CLKMASK) {
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case S5PV210_UCON_PCLK:
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clk->name = "pclk";
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break;
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case S5PV210_UCON_UCLK:
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clk->name = "uclk1";
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break;
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}
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return 0;
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}
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static int s5pv210_serial_resetport(struct uart_port *port,
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struct s3c2410_uartcfg *cfg)
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{
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unsigned long ucon = rd_regl(port, S3C2410_UCON);
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ucon &= S5PV210_UCON_CLKMASK;
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wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
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wr_regl(port, S3C2410_ULCON, cfg->ulcon);
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/* reset both fifos */
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wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
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wr_regl(port, S3C2410_UFCON, cfg->ufcon);
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return 0;
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}
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#define S5PV210_UART_DEFAULT_INFO(fifo_size) \
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.name = "Samsung S5PV210 UART0", \
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.type = PORT_S3C6400, \
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.fifosize = fifo_size, \
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.has_divslot = 1, \
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.rx_fifomask = S5PV210_UFSTAT_RXMASK, \
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.rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
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.rx_fifofull = S5PV210_UFSTAT_RXFULL, \
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.tx_fifofull = S5PV210_UFSTAT_TXFULL, \
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.tx_fifomask = S5PV210_UFSTAT_TXMASK, \
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.tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
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.get_clksrc = s5pv210_serial_getsource, \
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.set_clksrc = s5pv210_serial_setsource, \
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.reset_port = s5pv210_serial_resetport
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static struct s3c24xx_uart_info s5p_port_fifo256 = {
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S5PV210_UART_DEFAULT_INFO(256),
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};
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static struct s3c24xx_uart_info s5p_port_fifo64 = {
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S5PV210_UART_DEFAULT_INFO(64),
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};
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static struct s3c24xx_uart_info s5p_port_fifo16 = {
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S5PV210_UART_DEFAULT_INFO(16),
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};
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static struct s3c24xx_uart_info *s5p_uart_inf[] = {
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[0] = &s5p_port_fifo256,
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[1] = &s5p_port_fifo64,
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[2] = &s5p_port_fifo16,
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[3] = &s5p_port_fifo16,
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};
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/* device management */
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static int s5p_serial_probe(struct platform_device *pdev)
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{
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return s3c24xx_serial_probe(pdev, s5p_uart_inf[pdev->id]);
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}
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static struct platform_driver s5p_serial_drv = {
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.probe = s5p_serial_probe,
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.remove = __devexit_p(s3c24xx_serial_remove),
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.driver = {
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.name = "s5pv210-uart",
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.owner = THIS_MODULE,
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},
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};
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static int __init s5pv210_serial_console_init(void)
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{
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return s3c24xx_serial_initconsole(&s5p_serial_drv, s5p_uart_inf);
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}
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console_initcall(s5pv210_serial_console_init);
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static int __init s5p_serial_init(void)
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{
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return s3c24xx_serial_init(&s5p_serial_drv, *s5p_uart_inf);
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}
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static void __exit s5p_serial_exit(void)
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{
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platform_driver_unregister(&s5p_serial_drv);
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}
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module_init(s5p_serial_init);
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module_exit(s5p_serial_exit);
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:s5pv210-uart");
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MODULE_DESCRIPTION("Samsung S5PV210 UART Driver support");
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MODULE_AUTHOR("Thomas Abraham <[email protected]>");
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|
|
@ -1374,7 +1374,7 @@ s3c24xx_serial_get_options(struct uart_port *port, int *baud,
|
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* data.
|
||||
*/
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|
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static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
|
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static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info **info)
|
||||
{
|
||||
struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
|
||||
struct platform_device **platdev_ptr;
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||||
|
|
@ -1385,7 +1385,7 @@ static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
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|||
platdev_ptr = s3c24xx_uart_devs;
|
||||
|
||||
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
|
||||
s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
|
||||
s3c24xx_serial_init_port(ptr, info[i], *platdev_ptr);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -1451,7 +1451,7 @@ static struct console s3c24xx_serial_console = {
|
|||
};
|
||||
|
||||
int s3c24xx_serial_initconsole(struct platform_driver *drv,
|
||||
struct s3c24xx_uart_info *info)
|
||||
struct s3c24xx_uart_info **info)
|
||||
|
||||
{
|
||||
struct platform_device *dev = s3c24xx_uart_devs[0];
|
||||
|
|
|
|||
|
|
@ -75,19 +75,24 @@ extern int s3c24xx_serial_probe(struct platform_device *dev,
|
|||
extern int __devexit s3c24xx_serial_remove(struct platform_device *dev);
|
||||
|
||||
extern int s3c24xx_serial_initconsole(struct platform_driver *drv,
|
||||
struct s3c24xx_uart_info *uart);
|
||||
struct s3c24xx_uart_info **uart);
|
||||
|
||||
extern int s3c24xx_serial_init(struct platform_driver *drv,
|
||||
struct s3c24xx_uart_info *info);
|
||||
|
||||
#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
|
||||
|
||||
#define s3c24xx_console_init(__drv, __inf) \
|
||||
static int __init s3c_serial_console_init(void) \
|
||||
{ \
|
||||
return s3c24xx_serial_initconsole(__drv, __inf); \
|
||||
} \
|
||||
\
|
||||
#define s3c24xx_console_init(__drv, __inf) \
|
||||
static int __init s3c_serial_console_init(void) \
|
||||
{ \
|
||||
struct s3c24xx_uart_info *uinfo[CONFIG_SERIAL_SAMSUNG_UARTS]; \
|
||||
int i; \
|
||||
\
|
||||
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) \
|
||||
uinfo[i] = __inf; \
|
||||
return s3c24xx_serial_initconsole(__drv, uinfo); \
|
||||
} \
|
||||
\
|
||||
console_initcall(s3c_serial_console_init)
|
||||
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -30,7 +30,8 @@
|
|||
*/
|
||||
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_ARCH_SHMOBILE)
|
||||
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define PORT_PTCR 0xA405011EUL
|
||||
# define PORT_PVCR 0xA4050122UL
|
||||
|
|
@ -228,7 +229,8 @@
|
|||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_ARCH_SHMOBILE)
|
||||
# define SCIF_ORER 0x0200
|
||||
# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
|
||||
# define SCIF_RFDC_MASK 0x007f
|
||||
|
|
@ -261,7 +263,8 @@
|
|||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_ARCH_SHMOBILE)
|
||||
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
|
||||
# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
|
||||
# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
|
||||
|
|
@ -356,7 +359,7 @@
|
|||
SCI_OUT(sci_size, sci_offset, value); \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_SH3
|
||||
#if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SHMOBILE)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
|
||||
|
|
@ -366,7 +369,8 @@
|
|||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_ARCH_SHMOBILE)
|
||||
#define SCIF_FNS(name, scif_offset, scif_size) \
|
||||
CPU_SCIF_FNS(name, scif_offset, scif_size)
|
||||
#else
|
||||
|
|
@ -401,7 +405,8 @@
|
|||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_ARCH_SHMOBILE)
|
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SCIF_FNS(SCSMR, 0x00, 16)
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SCIF_FNS(SCBRR, 0x04, 8)
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@ -413,7 +418,7 @@ SCIF_FNS(SCFCR, 0x18, 16)
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SCIF_FNS(SCFDR, 0x1c, 16)
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SCIF_FNS(SCxTDR, 0x20, 8)
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SCIF_FNS(SCxRDR, 0x24, 8)
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SCIF_FNS(SCLSR, 0x24, 16)
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SCIF_FNS(SCLSR, 0x00, 0)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
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defined(CONFIG_CPU_SUBTYPE_SH7724)
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SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
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@ -583,7 +588,8 @@ static inline int sci_rxd_in(struct uart_port *port)
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_ARCH_SHMOBILE)
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#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
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defined(CONFIG_CPU_SUBTYPE_SH7724)
|
||||
|
|
|
|||
Loading…
Reference in a new issue