From dd31ba30eb4d0ac32ebfade3877e8e16a4b840e2 Mon Sep 17 00:00:00 2001
From: Wenjun Zhang <c_wjzhan@qti.qualcomm.com>
Date: Fri, 7 Aug 2020 13:42:56 +0800
Subject: [PATCH] ARM: dts: msm: enable lt9611uxc for hdk8350

Add lt9611uxc pincttl and dts configure.

Change-Id: I9c559051a4779e3b41c6cdc941c3f7fa00765e24
---
 qcom/lahaina-hdk.dtsi     | 103 ++++++++++++++++++++++++++++++++++++++
 qcom/lahaina-pinctrl.dtsi |  13 +++++
 2 files changed, 116 insertions(+)

diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi
index 5b02c6e0b39f..005e4ff816c5 100644
--- a/qcom/lahaina-hdk.dtsi
+++ b/qcom/lahaina-hdk.dtsi
@@ -81,3 +81,106 @@
 &sdhc_2 {
 	cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
 };
+
+&qupv3_se15_i2c {
+	status = "ok";
+
+	lt9611: lt,lt9611@2b {
+		compatible = "lt,lt9611uxc";
+		reg = <0x2b>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <50 0>;
+		interrupt-names = "lt_irq";
+		lt,irq-gpio = <&tlmm 50 0x0>;
+		lt,reset-gpio = <&tlmm 48 0x0>;
+		lt,hdmi-3p3-en = <&tlmm 47 0x0>;
+		lt,hdmi-1p2-en = <&tlmm 49 0x0>;
+		lt,non-pluggable;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&lt9611_pins>;
+
+		lt,preferred-mode = "1920x1080";
+
+		lt,customize-modes {
+			lt,customize-mode-id@0 {
+				lt,mode-h-active = <1920>;
+				lt,mode-h-front-porch = <88>;
+				lt,mode-h-pulse-width = <44>;
+				lt,mode-h-back-porch = <148>;
+				lt,mode-h-active-high;
+				lt,mode-v-active = <1080>;
+				lt,mode-v-front-porch = <4>;
+				lt,mode-v-pulse-width = <5>;
+				lt,mode-v-back-porch = <36>;
+				lt,mode-v-active-high;
+				lt,mode-refresh-rate = <60>;
+				lt,mode-clock-in-khz = <148500>;
+			};
+
+			lt,customize-mode-id@1 {
+				lt,mode-h-active = <3840>;
+				lt,mode-h-front-porch = <176>;
+				lt,mode-h-pulse-width = <88>;
+				lt,mode-h-back-porch = <400>;
+				lt,mode-h-active-high;
+				lt,mode-v-active = <2160>;
+				lt,mode-v-front-porch = <8>;
+				lt,mode-v-pulse-width = <10>;
+				lt,mode-v-back-porch = <72>;
+				lt,mode-v-active-high;
+				lt,mode-refresh-rate = <60>;
+				lt,mode-clock-in-khz = <608040>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				lt9611_in_0: endpoint {
+					remote-endpoint = <&ext_dsi_0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				lt9611_in_1: endpoint {
+					remote-endpoint = <&ext_dsi_1_out>;
+				};
+			};
+		};
+	};
+};
+
+&sde_dsi {
+	qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			ext_dsi_0_out: endpoint {
+				remote-endpoint = <&lt9611_in_0>;
+			};
+		};
+	};
+};
+
+&sde_dsi1 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+			ext_dsi_1_out: endpoint {
+				remote-endpoint = <&lt9611_in_1>;
+			};
+		};
+	};
+};
diff --git a/qcom/lahaina-pinctrl.dtsi b/qcom/lahaina-pinctrl.dtsi
index 4da16fb2cccb..3c81288625d9 100644
--- a/qcom/lahaina-pinctrl.dtsi
+++ b/qcom/lahaina-pinctrl.dtsi
@@ -380,6 +380,19 @@
 		};
 	};
 
+	lt9611_pins: lt9611_pins {
+		mux {
+			pins = "gpio47", "gpio48", "gpio49", "gpio50";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio47", "gpio48", "gpio49", "gpio50";
+			drive-strength = <8>;
+			bias-disable = <0>;
+		};
+	};
+
 	nfc {
 			nfc_int_active: nfc_int_active {
 				/* active state */