A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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ARM: dts: msm: Add cpufreq HW device node SDMSHRIKE

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Add cpufreq HW device node to scale 4 domain-0 & 4 domain-1 cores
on SDMSHRIKE SoCs.

Change-Id: I2cf89a059d028ed559623dba0d4abebfc1fe4c85
This commit is contained in:
Veera Vegivada 2020-12-17 14:28:23 +05:30
commit dd51641fbd
1 changed files with 17 additions and 0 deletions
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17
qcom/sdmshrike.dtsi
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@ -39,6 +39,7 @@
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
@ -72,6 +73,7 @@
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
@ -99,6 +101,7 @@
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_2>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
@ -126,6 +129,7 @@
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_3>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
#cooling-cells = <2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
@ -153,6 +157,7 @@
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_4>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
@ -180,6 +185,7 @@
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_5>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
@ -207,6 +213,7 @@
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_6>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
@ -234,6 +241,7 @@
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_7>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
@ -948,6 +956,15 @@
#clock-cells = <1>;
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <2>;
};
tcsr_mutex_block: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;