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msm: kgsl: constify structs with function pointers

Browse source 
Now that the last of the runtime modifications to adreno_gpudev are gone
finally mark it and the other structs as const to protect the function
pointers within.

Change-Id: Ic0dedbad25b39b5df0fdd565a494164e1588c9a1
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
This commit is contained in:
Jordan Crouse 2020-09-30 11:08:53 -06:00
commit ddb4927761
22 changed files with 100 additions and 99 deletions
Download patch file Download diff file Expand all files Collapse all files

42
drivers/gpu/msm/adreno.c
View file

@ -145,7 +145,7 @@ void adreno_reglist_write(struct adreno_device *adreno_dev,
void adreno_readreg64(struct adreno_device *adreno_dev,
enum adreno_regs lo, enum adreno_regs hi, uint64_t *val)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned int val_lo = 0, val_hi = 0;
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -168,7 +168,7 @@ void adreno_readreg64(struct adreno_device *adreno_dev,
void adreno_writereg64(struct adreno_device *adreno_dev,
enum adreno_regs lo, enum adreno_regs hi, uint64_t val)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (adreno_checkreg_off(adreno_dev, lo))
kgsl_regwrite(KGSL_DEVICE(adreno_dev),
@ -283,7 +283,7 @@ static int _get_counter(struct adreno_device *adreno_dev,
*/
void adreno_fault_detect_start(struct adreno_device *adreno_dev)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned int i, j = ARRAY_SIZE(adreno_ft_regs_default);
if (!test_bit(ADRENO_DEVICE_SOFT_FAULT_DETECT, &adreno_dev->priv))
@ -311,7 +311,7 @@ void adreno_fault_detect_start(struct adreno_device *adreno_dev)
*/
void adreno_fault_detect_stop(struct adreno_device *adreno_dev)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned int i, j = ARRAY_SIZE(adreno_ft_regs_default);
if (!test_bit(ADRENO_DEVICE_SOFT_FAULT_DETECT, &adreno_dev->priv))
@ -508,7 +508,7 @@ static struct input_handler adreno_input_handler = {
*/
static void _soft_reset(struct adreno_device *adreno_dev)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned int reg;
adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 1);
@ -571,7 +571,7 @@ void adreno_cp_callback(struct adreno_device *adreno_dev, int bit)
static irqreturn_t adreno_irq_handler(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
irqreturn_t ret;
atomic_inc(&adreno_dev->pending_irq_refcnt);
@ -590,7 +590,7 @@ static irqreturn_t adreno_irq_handler(struct kgsl_device *device)
}
irqreturn_t adreno_irq_callbacks(struct adreno_device *adreno_dev,
struct adreno_irq_funcs *funcs, u32 status)
const struct adreno_irq_funcs *funcs, u32 status)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
irqreturn_t ret = IRQ_NONE;
@ -1493,7 +1493,7 @@ static void adreno_unbind(struct device *dev)
{
struct adreno_device *adreno_dev;
struct kgsl_device *device;
struct adreno_gpudev *gpudev;
const struct adreno_gpudev *gpudev;
device = dev_get_drvdata(dev);
if (!device)
@ -1612,7 +1612,7 @@ static int adreno_pm_suspend(struct device *dev)
static void adreno_fault_detect_init(struct adreno_device *adreno_dev)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
int i;
if (!ADRENO_FEATURE(adreno_dev, ADRENO_SOFT_FAULT_DETECT))
@ -1651,7 +1651,7 @@ static void adreno_fault_detect_init(struct adreno_device *adreno_dev)
static int adreno_init(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
int ret;
ret = kgsl_pwrctrl_change_state(device, KGSL_STATE_INIT);
@ -2003,7 +2003,7 @@ void adreno_clear_dcvs_counters(struct adreno_device *adreno_dev)
static int _adreno_start(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
int status;
unsigned int state = device->state;
bool regulator_left_on;
@ -2126,7 +2126,7 @@ int adreno_start(struct kgsl_device *device, int priority)
static int adreno_stop(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
int error = 0;
if (!test_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv))
@ -2174,7 +2174,7 @@ static int adreno_stop(struct kgsl_device *device)
int adreno_reset(struct kgsl_device *device, int fault)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
int ret = -EINVAL;
int i;
@ -2649,7 +2649,7 @@ bool adreno_irq_pending(struct adreno_device *adreno_dev)
static int adreno_soft_reset(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
int ret;
/*
@ -2722,7 +2722,7 @@ static int adreno_soft_reset(struct kgsl_device *device)
static bool adreno_isidle(struct adreno_device *adreno_dev)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct adreno_ringbuffer *rb;
int i;
@ -2983,7 +2983,7 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,
unsigned int fence_mask)
{
unsigned int status, i;
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned int reg_offset = gpudev->reg_offsets[offset];
adreno_writereg(adreno_dev, offset, val);
@ -3382,7 +3382,7 @@ static void adreno_power_stats(struct kgsl_device *device,
struct kgsl_power_stats *stats)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
struct adreno_busy_data *busy = &adreno_dev->busy_data;
int64_t adj = 0;
@ -3504,7 +3504,7 @@ static int adreno_regulator_enable(struct kgsl_device *device)
{
int ret = 0;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (gpudev->regulator_enable &&
!test_bit(ADRENO_DEVICE_GPU_REGULATOR_ENABLED,
@ -3520,7 +3520,7 @@ static int adreno_regulator_enable(struct kgsl_device *device)
static bool adreno_is_hw_collapsible(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
/*
* Skip power collapse for A304, if power ctrl flag is set to
@ -3538,7 +3538,7 @@ static bool adreno_is_hw_collapsible(struct kgsl_device *device)
static void adreno_regulator_disable(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (gpudev->regulator_disable &&
test_bit(ADRENO_DEVICE_GPU_REGULATOR_ENABLED,
@ -3553,7 +3553,7 @@ static void adreno_pwrlevel_change_settings(struct kgsl_device *device,
unsigned int prelevel, unsigned int postlevel, bool post)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (gpudev->pwrlevel_change_settings)
gpudev->pwrlevel_change_settings(adreno_dev, prelevel,

32
drivers/gpu/msm/adreno.h
View file

@ -390,7 +390,7 @@ struct adreno_gpu_core {
*/
const char *compatible;
unsigned long features;
struct adreno_gpudev *gpudev;
const struct adreno_gpudev *gpudev;
const struct adreno_perfcounters *perfcounters;
unsigned long gmem_base;
size_t gmem_size;
@ -879,14 +879,14 @@ extern unsigned int *adreno_ft_regs;
extern unsigned int adreno_ft_regs_num;
extern unsigned int *adreno_ft_regs_val;
extern struct adreno_gpudev adreno_a3xx_gpudev;
extern struct adreno_gpudev adreno_a5xx_gpudev;
extern struct adreno_gpudev adreno_a6xx_gpudev;
extern struct adreno_gpudev adreno_a6xx_gmu_gpudev;
extern struct adreno_gpudev adreno_a6xx_rgmu_gpudev;
extern struct adreno_gpudev adreno_a619_holi_gpudev;
extern struct adreno_gpudev adreno_a630_gpudev;
extern struct adreno_gpudev adreno_a6xx_hwsched_gpudev;
extern const struct adreno_gpudev adreno_a3xx_gpudev;
extern const struct adreno_gpudev adreno_a5xx_gpudev;
extern const struct adreno_gpudev adreno_a6xx_gpudev;
extern const struct adreno_gpudev adreno_a6xx_gmu_gpudev;
extern const struct adreno_gpudev adreno_a6xx_rgmu_gpudev;
extern const struct adreno_gpudev adreno_a619_holi_gpudev;
extern const struct adreno_gpudev adreno_a630_gpudev;
extern const struct adreno_gpudev adreno_a6xx_hwsched_gpudev;
extern int adreno_wake_nice;
extern unsigned int adreno_wake_timeout;
@ -1133,7 +1133,7 @@ static inline int adreno_is_a640v2(struct adreno_device *adreno_dev)
static inline bool adreno_checkreg_off(struct adreno_device *adreno_dev,
enum adreno_regs offset_name)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (offset_name >= ADRENO_REG_REGISTER_MAX ||
gpudev->reg_offsets[offset_name] == ADRENO_REG_UNUSED)
@ -1163,7 +1163,7 @@ static inline bool adreno_checkreg_off(struct adreno_device *adreno_dev,
static inline void adreno_readreg(struct adreno_device *adreno_dev,
enum adreno_regs offset_name, unsigned int *val)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (adreno_checkreg_off(adreno_dev, offset_name))
kgsl_regread(KGSL_DEVICE(adreno_dev),
@ -1182,7 +1182,7 @@ static inline void adreno_readreg(struct adreno_device *adreno_dev,
static inline void adreno_writereg(struct adreno_device *adreno_dev,
enum adreno_regs offset_name, unsigned int val)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (adreno_checkreg_off(adreno_dev, offset_name))
kgsl_regwrite(KGSL_DEVICE(adreno_dev),
@ -1198,7 +1198,7 @@ static inline void adreno_writereg(struct adreno_device *adreno_dev,
static inline unsigned int adreno_getreg(struct adreno_device *adreno_dev,
enum adreno_regs offset_name)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (!adreno_checkreg_off(adreno_dev, offset_name))
return ADRENO_REG_REGISTER_MAX;
@ -1215,7 +1215,7 @@ static inline unsigned int adreno_getreg(struct adreno_device *adreno_dev,
static inline void adreno_read_gmureg(struct adreno_device *adreno_dev,
enum adreno_regs offset_name, unsigned int *val)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (adreno_checkreg_off(adreno_dev, offset_name))
gmu_core_regread(KGSL_DEVICE(adreno_dev),
@ -1234,7 +1234,7 @@ static inline void adreno_read_gmureg(struct adreno_device *adreno_dev,
static inline void adreno_write_gmureg(struct adreno_device *adreno_dev,
enum adreno_regs offset_name, unsigned int val)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (adreno_checkreg_off(adreno_dev, offset_name))
gmu_core_regwrite(KGSL_DEVICE(adreno_dev),
@ -1791,7 +1791,7 @@ int adreno_zap_shader_load(struct adreno_device *adreno_dev,
* Return: IRQ_HANDLED if one or more interrupt callbacks were called.
*/
irqreturn_t adreno_irq_callbacks(struct adreno_device *adreno_dev,
struct adreno_irq_funcs *funcs, u32 status);
const struct adreno_irq_funcs *funcs, u32 status);
/**

4
drivers/gpu/msm/adreno_a3xx.c
View file

@ -793,7 +793,7 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit)
(1 << A3XX_INT_CP_AHB_ERROR_HALT) | \
(1 << A3XX_INT_UCHE_OOB_ACCESS))
static struct adreno_irq_funcs a3xx_irq_funcs[32] = {
static const struct adreno_irq_funcs a3xx_irq_funcs[32] = {
ADRENO_IRQ_CALLBACK(NULL), /* 0 - RBBM_GPU_IDLE */
ADRENO_IRQ_CALLBACK(a3xx_err_callback), /* 1 - RBBM_AHB_ERROR */
ADRENO_IRQ_CALLBACK(NULL), /* 2 - RBBM_REG_TIMEOUT */
@ -1241,7 +1241,7 @@ static int a3xx_clear_pending_transactions(struct adreno_device *adreno_dev)
return ret;
}
struct adreno_gpudev adreno_a3xx_gpudev = {
const struct adreno_gpudev adreno_a3xx_gpudev = {
.reg_offsets = a3xx_register_offsets,
.ft_perf_counters = a3xx_ft_perf_counters,
.ft_perf_counters_count = ARRAY_SIZE(a3xx_ft_perf_counters),

4
drivers/gpu/msm/adreno_a5xx.c
View file

@ -2343,7 +2343,7 @@ u64 a5xx_read_alwayson(struct adreno_device *adreno_dev)
}
static struct adreno_irq_funcs a5xx_irq_funcs[32] = {
static const struct adreno_irq_funcs a5xx_irq_funcs[32] = {
ADRENO_IRQ_CALLBACK(NULL), /* 0 - RBBM_GPU_IDLE */
ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 1 - RBBM_AHB_ERROR */
ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 2 - RBBM_TRANSFER_TIMEOUT */
@ -2646,7 +2646,7 @@ static struct adreno_coresight a5xx_coresight = {
};
#endif
struct adreno_gpudev adreno_a5xx_gpudev = {
const struct adreno_gpudev adreno_a5xx_gpudev = {
.reg_offsets = a5xx_register_offsets,
#ifdef CONFIG_QCOM_KGSL_CORESIGHT
.coresight = {&a5xx_coresight},

16
drivers/gpu/msm/adreno_a6xx.c
View file

@ -1585,7 +1585,7 @@ static void a6xx_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)
adreno_dispatcher_schedule(device);
}
static struct adreno_irq_funcs a6xx_irq_funcs[32] = {
static const struct adreno_irq_funcs a6xx_irq_funcs[32] = {
ADRENO_IRQ_CALLBACK(NULL), /* 0 - RBBM_GPU_IDLE */
ADRENO_IRQ_CALLBACK(a6xx_err_callback), /* 1 - RBBM_AHB_ERROR */
ADRENO_IRQ_CALLBACK(NULL), /* 2 - UNUSED */
@ -2123,7 +2123,7 @@ int a6xx_probe_common(struct platform_device *pdev,
struct adreno_device *adreno_dev, u32 chipid,
const struct adreno_gpu_core *gpucore)
{
struct adreno_gpudev *gpudev = gpucore->gpudev;
const struct adreno_gpudev *gpudev = gpucore->gpudev;
adreno_dev->gpucore = gpucore;
adreno_dev->chipid = chipid;
@ -2464,7 +2464,7 @@ static int a6xx_clear_pending_transactions(struct adreno_device *adreno_dev)
return a6xx_halt_gbif(adreno_dev);
}
struct adreno_gpudev adreno_a6xx_gpudev = {
const struct adreno_gpudev adreno_a6xx_gpudev = {
.reg_offsets = a6xx_register_offsets,
.probe = a6xx_probe,
.start = a6xx_start,
@ -2499,7 +2499,7 @@ struct adreno_gpudev adreno_a6xx_gpudev = {
.clear_pending_transactions = a6xx_clear_pending_transactions,
};
struct adreno_gpudev adreno_a6xx_hwsched_gpudev = {
const struct adreno_gpudev adreno_a6xx_hwsched_gpudev = {
.reg_offsets = a6xx_register_offsets,
.probe = a6xx_hwsched_probe,
.snapshot = a6xx_hwsched_snapshot,
@ -2515,7 +2515,7 @@ struct adreno_gpudev adreno_a6xx_hwsched_gpudev = {
.power_ops = &a6xx_hwsched_power_ops,
};
struct adreno_gpudev adreno_a6xx_gmu_gpudev = {
const struct adreno_gpudev adreno_a6xx_gmu_gpudev = {
.reg_offsets = a6xx_register_offsets,
.probe = a6xx_gmu_device_probe,
.start = a6xx_start,
@ -2546,7 +2546,7 @@ struct adreno_gpudev adreno_a6xx_gmu_gpudev = {
.power_ops = &a6xx_gmu_power_ops,
};
struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {
const struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {
.reg_offsets = a6xx_register_offsets,
.probe = a6xx_rgmu_device_probe,
.start = a6xx_start,
@ -2577,7 +2577,7 @@ struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {
.power_ops = &a6xx_rgmu_power_ops,
};
struct adreno_gpudev adreno_a619_holi_gpudev = {
const struct adreno_gpudev adreno_a619_holi_gpudev = {
.reg_offsets = a6xx_register_offsets,
.probe = a6xx_probe,
.start = a6xx_start,
@ -2612,7 +2612,7 @@ struct adreno_gpudev adreno_a619_holi_gpudev = {
.clear_pending_transactions = a6xx_clear_pending_transactions,
};
struct adreno_gpudev adreno_a630_gpudev = {
const struct adreno_gpudev adreno_a630_gpudev = {
.reg_offsets = a6xx_register_offsets,
.probe = a6xx_gmu_device_probe,
.start = a6xx_start,

2
drivers/gpu/msm/adreno_a6xx_gmu.c
View file

@ -2351,7 +2351,7 @@ static int a6xx_gmu_acd_set(struct kgsl_device *device, bool val)
return adreno_power_cycle(adreno_dev, set_acd, &val);
}
static struct gmu_dev_ops a6xx_gmudev = {
static const struct gmu_dev_ops a6xx_gmudev = {
.oob_set = a6xx_gmu_oob_set,
.oob_clear = a6xx_gmu_oob_clear,
.gx_is_on = a6xx_gmu_gx_is_on,

2
drivers/gpu/msm/adreno_a6xx_rgmu.c
View file

@ -1191,7 +1191,7 @@ static void a6xx_rgmu_pm_resume(struct adreno_device *adreno_dev)
adreno_dispatcher_start(device);
}
static struct gmu_dev_ops a6xx_rgmudev = {
static const struct gmu_dev_ops a6xx_rgmudev = {
.oob_set = a6xx_rgmu_oob_set,
.oob_clear = a6xx_rgmu_oob_clear,
.gx_is_on = a6xx_rgmu_gx_is_on,

2
drivers/gpu/msm/adreno_a6xx_snapshot.c
View file

@ -1732,7 +1732,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev,
struct kgsl_snapshot *snapshot)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct adreno_ringbuffer *rb;
bool sptprac_on = true;
unsigned int i, roq_size;

12
drivers/gpu/msm/adreno_coresight.c
View file

@ -144,7 +144,7 @@ static void adreno_coresight_disable(struct coresight_device *csdev,
{
struct kgsl_device *device = dev_get_drvdata(csdev->dev.parent);
struct adreno_device *adreno_dev;
struct adreno_gpudev *gpudev;
const struct adreno_gpudev *gpudev;
struct adreno_coresight *coresight;
int i, cs_id;
@ -191,7 +191,7 @@ static int _adreno_coresight_get_and_clear(struct adreno_device *adreno_dev,
int cs_id)
{
int i;
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_coresight *coresight = gpudev->coresight[cs_id];
@ -225,7 +225,7 @@ static int _adreno_coresight_get_and_clear(struct adreno_device *adreno_dev,
static int _adreno_coresight_set(struct adreno_device *adreno_dev, int cs_id)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_coresight *coresight = gpudev->coresight[cs_id];
int i;
@ -251,7 +251,7 @@ static int adreno_coresight_enable(struct coresight_device *csdev,
{
struct kgsl_device *device = dev_get_drvdata(csdev->dev.parent);
struct adreno_device *adreno_dev;
struct adreno_gpudev *gpudev;
const struct adreno_gpudev *gpudev;
struct adreno_coresight *coresight;
int ret = 0, adreno_dev_flag = -EINVAL, cs_id;
@ -323,7 +323,7 @@ void adreno_coresight_start(struct adreno_device *adreno_dev)
static int adreno_coresight_trace_id(struct coresight_device *csdev)
{
struct kgsl_device *device = dev_get_drvdata(csdev->dev.parent);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(ADRENO_DEVICE(device));
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(ADRENO_DEVICE(device));
int cs_id;
cs_id = adreno_coresight_identify(dev_name(&csdev->dev));
@ -386,7 +386,7 @@ adreno_coresight_dev_probe(struct kgsl_device *device,
void adreno_coresight_init(struct adreno_device *adreno_dev)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
int i = 0;
struct device_node *node, *child;

6
drivers/gpu/msm/adreno_dispatch.c
View file

@ -570,7 +570,7 @@ static int sendcmd(struct adreno_device *adreno_dev,
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct kgsl_drawobj *drawobj = DRAWOBJ(cmdobj);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct adreno_dispatcher *dispatcher = &adreno_dev->dispatcher;
struct adreno_context *drawctxt = ADRENO_CONTEXT(drawobj->context);
struct kgsl_context *context = drawobj->context;
@ -2055,7 +2055,7 @@ static void do_header_and_snapshot(struct kgsl_device *device, int fault,
static int dispatcher_do_fault(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct adreno_dispatcher *dispatcher = &adreno_dev->dispatcher;
struct adreno_dispatcher_drawqueue *dispatch_q = NULL, *dispatch_q_temp;
struct adreno_ringbuffer *rb;
@ -2495,7 +2495,7 @@ static void adreno_dispatcher_work(struct kthread_work *work)
struct adreno_device *adreno_dev =
container_of(dispatcher, struct adreno_device, dispatcher);
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
int count = 0;
unsigned int i = 0;

4
drivers/gpu/msm/adreno_drawctxt.c
View file

@ -311,7 +311,7 @@ adreno_drawctxt_create(struct kgsl_device_private *dev_priv,
struct adreno_context *drawctxt;
struct kgsl_device *device = dev_priv->device;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
int ret;
unsigned int local;
@ -491,7 +491,7 @@ void adreno_drawctxt_detach(struct kgsl_context *context)
{
struct kgsl_device *device;
struct adreno_device *adreno_dev;
struct adreno_gpudev *gpudev;
const struct adreno_gpudev *gpudev;
struct adreno_context *drawctxt;
int count, i;
struct kgsl_drawobj *list[ADRENO_CONTEXT_DRAWQUEUE_SIZE];

8
drivers/gpu/msm/adreno_ringbuffer.c
View file

@ -32,7 +32,7 @@ static void adreno_get_submit_time(struct adreno_device *adreno_dev,
struct adreno_ringbuffer *rb,
struct adreno_submit_time *time)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned long flags;
struct adreno_context *drawctxt = rb->drawctxt_active;
struct kgsl_context *context = &drawctxt->base;
@ -327,7 +327,7 @@ int adreno_ringbuffer_init(struct adreno_device *adreno_dev)
adreno_dev->cur_rb = &(adreno_dev->ringbuffers[0]);
if (ADRENO_FEATURE(adreno_dev, ADRENO_PREEMPTION)) {
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct adreno_preemption *preempt = &adreno_dev->preempt;
int ret;
@ -399,7 +399,7 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
struct adreno_submit_time *time)
{
struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
unsigned int *ringcmds, *start;
unsigned int total_sizedwords = sizedwords;
@ -856,7 +856,7 @@ int adreno_ringbuffer_submitcmd(struct adreno_device *adreno_dev,
struct adreno_submit_time *time)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct kgsl_drawobj *drawobj = DRAWOBJ(cmdobj);
struct kgsl_memobj_node *ib;
unsigned int numibs = 0;

2
drivers/gpu/msm/adreno_snapshot.c
View file

@ -816,7 +816,7 @@ void adreno_snapshot(struct kgsl_device *device, struct kgsl_snapshot *snapshot,
{
unsigned int i;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
ib_max_objs = 0;
/* Reset the list of objects */

9
drivers/gpu/msm/adreno_sysfs.c
View file

@ -192,7 +192,7 @@ ssize_t adreno_sysfs_store_u32(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(dev_get_drvdata(dev));
struct adreno_sysfs_attribute_u32 *_attr =
const struct adreno_sysfs_attribute_u32 *_attr =
container_of(attr, struct adreno_sysfs_attribute_u32, attr);
u32 val;
int ret;
@ -212,7 +212,7 @@ ssize_t adreno_sysfs_show_u32(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(dev_get_drvdata(dev));
struct adreno_sysfs_attribute_u32 *_attr =
const struct adreno_sysfs_attribute_u32 *_attr =
container_of(attr, struct adreno_sysfs_attribute_u32, attr);
return scnprintf(buf, PAGE_SIZE, "0x%X\n", _attr->show(adreno_dev));
@ -222,7 +222,7 @@ ssize_t adreno_sysfs_store_bool(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(dev_get_drvdata(dev));
struct adreno_sysfs_attribute_bool *_attr =
const struct adreno_sysfs_attribute_bool *_attr =
container_of(attr, struct adreno_sysfs_attribute_bool, attr);
bool val;
int ret;
@ -242,11 +242,12 @@ ssize_t adreno_sysfs_show_bool(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(dev_get_drvdata(dev));
struct adreno_sysfs_attribute_bool *_attr =
const struct adreno_sysfs_attribute_bool *_attr =
container_of(attr, struct adreno_sysfs_attribute_bool, attr);
return scnprintf(buf, PAGE_SIZE, "%d\n", _attr->show(adreno_dev));
}
static ADRENO_SYSFS_U32(ft_policy);
static ADRENO_SYSFS_U32(ft_pagefault_policy);
static ADRENO_SYSFS_BOOL(ft_long_ib_detect);

8
drivers/gpu/msm/adreno_sysfs.h
View file

@ -49,7 +49,7 @@ ssize_t adreno_sysfs_show_bool(struct device *dev,
struct device_attribute *attr, char *buf);
#define ADRENO_SYSFS_BOOL(_name) \
struct adreno_sysfs_attribute_bool adreno_attr_##_name = { \
const struct adreno_sysfs_attribute_bool adreno_attr_##_name = { \
.attr = __ATTR(_name, 0644, adreno_sysfs_show_bool, \
adreno_sysfs_store_bool), \
.show = _ ## _name ## _show, \
@ -57,13 +57,13 @@ struct adreno_sysfs_attribute_bool adreno_attr_##_name = { \
}
#define ADRENO_SYSFS_RO_BOOL(_name) \
struct adreno_sysfs_attribute_bool adreno_attr_##_name = { \
const struct adreno_sysfs_attribute_bool adreno_attr_##_name = { \
.attr = __ATTR(_name, 0444, adreno_sysfs_show_bool, NULL), \
.show = _ ## _name ## _show, \
}
#define ADRENO_SYSFS_U32(_name) \
struct adreno_sysfs_attribute_u32 adreno_attr_##_name = { \
const struct adreno_sysfs_attribute_u32 adreno_attr_##_name = { \
.attr = __ATTR(_name, 0644, adreno_sysfs_show_u32, \
adreno_sysfs_store_u32), \
.show = _ ## _name ## _show, \
@ -71,7 +71,7 @@ struct adreno_sysfs_attribute_u32 adreno_attr_##_name = { \
}
#define ADRENO_SYSFS_RO_U32(_name) \
struct adreno_sysfs_attribute_u32 adreno_attr_##_name = { \
const struct adreno_sysfs_attribute_u32 adreno_attr_##_name = { \
.attr = __ATTR(_name, 0444, adreno_sysfs_show_u32, NULL), \
.show = _ ## _name ## _show, \
}

2
drivers/gpu/msm/kgsl.h
View file

@ -209,7 +209,7 @@ struct kgsl_memdesc {
uint64_t mapsize;
unsigned int priv;
struct sg_table *sgt;
struct kgsl_memdesc_ops *ops;
const struct kgsl_memdesc_ops *ops;
uint64_t flags;
struct device *dev;
unsigned long attrs;

18
drivers/gpu/msm/kgsl_gmu_core.c
View file

@ -56,7 +56,7 @@ bool gmu_core_gpmu_isenabled(struct kgsl_device *device)
bool gmu_core_scales_bandwidth(struct kgsl_device *device)
{
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
const struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
if (ops && ops->scales_bandwidth)
return ops->scales_bandwidth(device);
@ -66,7 +66,7 @@ bool gmu_core_scales_bandwidth(struct kgsl_device *device)
int gmu_core_dev_acd_set(struct kgsl_device *device, bool val)
{
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
const struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
if (ops && ops->acd_set)
return ops->acd_set(device, val);
@ -158,7 +158,7 @@ void gmu_core_regrmw(struct kgsl_device *device,
int gmu_core_dev_oob_set(struct kgsl_device *device, enum oob_request req)
{
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
const struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
if (ops && ops->oob_set)
return ops->oob_set(device, req);
@ -168,7 +168,7 @@ int gmu_core_dev_oob_set(struct kgsl_device *device, enum oob_request req)
void gmu_core_dev_oob_clear(struct kgsl_device *device, enum oob_request req)
{
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
const struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
if (ops && ops->oob_clear)
ops->oob_clear(device, req);
@ -177,7 +177,7 @@ void gmu_core_dev_oob_clear(struct kgsl_device *device, enum oob_request req)
void gmu_core_dev_cooperative_reset(struct kgsl_device *device)
{
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
const struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
if (ops && ops->cooperative_reset)
ops->cooperative_reset(device);
@ -185,7 +185,7 @@ void gmu_core_dev_cooperative_reset(struct kgsl_device *device)
bool gmu_core_dev_gx_is_on(struct kgsl_device *device)
{
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
const struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
if (ops && ops->gx_is_on)
return ops->gx_is_on(device);
@ -195,7 +195,7 @@ bool gmu_core_dev_gx_is_on(struct kgsl_device *device)
int gmu_core_dev_ifpc_show(struct kgsl_device *device)
{
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
const struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
if (ops && ops->ifpc_show)
return ops->ifpc_show(device);
@ -205,7 +205,7 @@ int gmu_core_dev_ifpc_show(struct kgsl_device *device)
int gmu_core_dev_ifpc_store(struct kgsl_device *device, unsigned int val)
{
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
const struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
if (ops && ops->ifpc_store)
return ops->ifpc_store(device, val);
@ -215,7 +215,7 @@ int gmu_core_dev_ifpc_store(struct kgsl_device *device, unsigned int val)
int gmu_core_dev_wait_for_active_transition(struct kgsl_device *device)
{
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
const struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
if (ops && ops->wait_for_active_transition)
return ops->wait_for_active_transition(device);

2
drivers/gpu/msm/kgsl_gmu_core.h
View file

@ -124,7 +124,7 @@ struct gmu_core_device {
unsigned int gmu2gpu_offset;
unsigned int reg_len;
void __iomem *reg_virt;
struct gmu_dev_ops *dev_ops;
const struct gmu_dev_ops *dev_ops;
unsigned long flags;
};

10
drivers/gpu/msm/kgsl_iommu.c
View file

@ -41,7 +41,7 @@
#define IDR1_NUMPAGENDXB GENMASK(30, 28)
#define IDR1_PAGESIZE BIT(31)
static struct kgsl_mmu_pt_ops iommu_pt_ops;
static const struct kgsl_mmu_pt_ops iommu_pt_ops;
/*
* struct kgsl_iommu_addr_entry - entry in the kgsl_iommu_pt rbtree.
@ -600,7 +600,7 @@ static int kgsl_iommu_fault_handler(struct iommu_domain *domain,
int write;
struct kgsl_device *device;
struct adreno_device *adreno_dev;
struct adreno_gpudev *gpudev;
const struct adreno_gpudev *gpudev;
unsigned int no_page_fault_log = 0;
char *fault_type = "unknown";
char *comm = "unknown";
@ -2368,7 +2368,7 @@ static const char * const kgsl_iommu_clocks[] = {
"gcc_gpu_axi_clk",
};
static struct kgsl_mmu_ops kgsl_iommu_ops;
static const struct kgsl_mmu_ops kgsl_iommu_ops;
int kgsl_iommu_probe(struct kgsl_device *device)
{
@ -2498,7 +2498,7 @@ err:
return ret;
}
static struct kgsl_mmu_ops kgsl_iommu_ops = {
static const struct kgsl_mmu_ops kgsl_iommu_ops = {
.mmu_close = kgsl_iommu_close,
.mmu_start = kgsl_iommu_start,
.mmu_set_pt = kgsl_iommu_set_pt,
@ -2514,7 +2514,7 @@ static struct kgsl_mmu_ops kgsl_iommu_ops = {
.mmu_map_global = kgsl_iommu_map_global,
};
static struct kgsl_mmu_pt_ops iommu_pt_ops = {
static const struct kgsl_mmu_pt_ops iommu_pt_ops = {
.mmu_map = kgsl_iommu_map,
.mmu_unmap = kgsl_iommu_unmap,
.mmu_destroy_pagetable = kgsl_iommu_destroy_pagetable,

2
drivers/gpu/msm/kgsl_mmu.c
View file

@ -530,7 +530,7 @@ static int nommu_get_gpuaddr(struct kgsl_pagetable *pagetable,
return -ENOMEM;
}
static struct kgsl_mmu_pt_ops nommu_pt_ops = {
static const struct kgsl_mmu_pt_ops nommu_pt_ops = {
.get_gpuaddr = nommu_get_gpuaddr,
.addr_in_range = nommu_gpuaddr_in_range,
};

10
drivers/gpu/msm/kgsl_sharedmem.c
View file

@ -957,25 +957,25 @@ static void kgsl_free_system_pages(struct kgsl_memdesc *memdesc)
memdesc->pages = NULL;
}
static struct kgsl_memdesc_ops kgsl_contiguous_ops = {
static const struct kgsl_memdesc_ops kgsl_contiguous_ops = {
.free = kgsl_contiguous_free,
.vmflags = VM_DONTDUMP | VM_PFNMAP | VM_DONTEXPAND | VM_DONTCOPY,
.vmfault = kgsl_contiguous_vmfault,
};
#if IS_ENABLED(CONFIG_QCOM_SECURE_BUFFER)
static struct kgsl_memdesc_ops kgsl_secure_system_ops = {
static const struct kgsl_memdesc_ops kgsl_secure_system_ops = {
.free = kgsl_free_secure_system_pages,
/* FIXME: Make sure vmflags / vmfault does the right thing here */
};
static struct kgsl_memdesc_ops kgsl_secure_pool_ops = {
static const struct kgsl_memdesc_ops kgsl_secure_pool_ops = {
.free = kgsl_free_secure_pool_pages,
/* FIXME: Make sure vmflags / vmfault does the right thing here */
};
#endif
static struct kgsl_memdesc_ops kgsl_pool_ops = {
static const struct kgsl_memdesc_ops kgsl_pool_ops = {
.free = kgsl_free_pool_pages,
.vmflags = VM_DONTDUMP | VM_DONTEXPAND | VM_DONTCOPY | VM_MIXEDMAP,
.vmfault = kgsl_paged_vmfault,
@ -983,7 +983,7 @@ static struct kgsl_memdesc_ops kgsl_pool_ops = {
.unmap_kernel = kgsl_paged_unmap_kernel,
};
static struct kgsl_memdesc_ops kgsl_system_ops = {
static const struct kgsl_memdesc_ops kgsl_system_ops = {
.free = kgsl_free_system_pages,
.vmflags = VM_DONTDUMP | VM_DONTEXPAND | VM_DONTCOPY | VM_MIXEDMAP,
.vmfault = kgsl_paged_vmfault,

2
drivers/gpu/msm/kgsl_sysfs.h
View file

@ -22,7 +22,7 @@ struct kgsl_gpu_sysfs_attr {
};
#define GPU_SYSFS_ATTR(_name, _mode, _show, _store) \
struct kgsl_gpu_sysfs_attr gpu_sysfs_attr_##_name = { \
const struct kgsl_gpu_sysfs_attr gpu_sysfs_attr_##_name = { \
.attr = { .name = __stringify(_name), .mode = _mode }, \
.show = _show, \
.store = _store, \