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ARM: dts: msm: Add UFS support for holi

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This change adds UFS support for holi platform.

Change-Id: Iaeafd650e890d3d97c7cf70f28d4ec47d89f08b7
This commit is contained in:
Nitin Rawat 2020-06-22 02:16:30 +05:30
commit ddf73d27c5
2 changed files with 99 additions and 0 deletions
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36
qcom/holi-rumi.dtsi
View file

@ -34,3 +34,39 @@
dr_mode = "peripheral";
};
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qrbtc-sdm845";
vdda-phy-supply = <&L18A>;
vdda-pll-supply = <&L22A>;
vdda-phy-max-microamp = <62900>;
vdda-pll-max-microamp = <18300>;
status = "ok"
};
&ufshc_mem {
limit-tx-hs-gear = <1>;
limit-rx-hs-gear = <1>;
limit-rate = <1>; /* HS Rate-B */
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vdd-hba-fixed-regulator;
vcc-supply = <&L7E>;
vcc-max-microamp = <800000>;
vccq2-supply = <&L12A>;
vccq2-max-microamp = <800000>;
qcom,vddp-ref-clk-supply = <&L22A>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,disable-lpm;
rpm-level = <0>;
spm-level = <0>;
status = "ok"
};

63
qcom/holi.dtsi
View file

@ -4,6 +4,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Holi";
@ -15,6 +16,10 @@
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
@ -929,6 +934,64 @@
qcom,firmware-name = "venus";
memory-region = <&pil_video_mem>;
};
ufsphy_mem: ufsphy_mem@4807000 {
reg = <0x4807000 0xDDC>;
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <1>;
clock-names = "ref_clk_src",
"ref_aux_clk";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufshc_mem 0>;
status = "disabled";
};
ufshc_mem: ufshc@4804000 {
compatible = "qcom,ufshc";
reg = <0x4804000 0x3000>;
reg-names = "ufs_mem";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
lanes-per-direction = <1>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
freq-table-hz =
<50000000 200000000>,
<0 0>,
<0 0>,
<37500000 150000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>;
reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>;
//resets = <&gcc GCC_UFS_PHY_BCR>;
//reset-names = "rst";
status = "disabled";
};
};
#define PMK8350_SID 6