From 900c6f988540881e413a56f0f5d6d44ad34c3de5 Mon Sep 17 00:00:00 2001 From: Vivek Aknurwar Date: Thu, 13 Feb 2020 13:41:06 -0800 Subject: [PATCH] clk: qcom: gcc-lahaina: Enable gpu_memnoc_gfx and gpu_snoc_dvm_gfx always SMMU hw voting did not tie these 2 clocks. Although these clocks are default enabled on boot, SW needs to explicitly make sure to keep them always enabled to keep smmu access. These clks will automatically turn on/off along with CX_GDSC so no power hit. Change-Id: I4fb82589f63c0a321465e249e54f94be7e5449a3 Signed-off-by: Vivek Aknurwar --- drivers/clk/qcom/gcc-lahaina.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-lahaina.c b/drivers/clk/qcom/gcc-lahaina.c index 4822d432ee9b..0c104af731eb 100644 --- a/drivers/clk/qcom/gcc-lahaina.c +++ b/drivers/clk/qcom/gcc-lahaina.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -2374,7 +2374,7 @@ static struct clk_branch gcc_gpu_memnoc_gfx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_memnoc_gfx_clk", - .ops = &clk_branch2_ops, + .ops = &clk_branch2_aon_ops, }, }, }; @@ -2387,7 +2387,7 @@ static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_snoc_dvm_gfx_clk", - .ops = &clk_branch2_ops, + .ops = &clk_branch2_aon_ops, }, }, };