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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-15 01:01:56 -04:00
asoc: qcs405: add support for dsd input
Update machine driver to include support for dsd input. Change-Id: I37aa46484aa617f3ea543391b0edec4f5193d5bf Signed-off-by: Sanjana B <sanjb@codeaurora.org>
This commit is contained in:
Sanjana B
Gerrit - the friendly Code Review server
parent
5fbd9fb16f
commit
df48f09425
1 changed files with 186 additions and 4 deletions
190
asoc/qcs405.c
190
asoc/qcs405.c
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@ -21,6 +21,7 @@
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#include <sound/pcm_params.h>
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#include <sound/info.h>
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#include <dsp/audio_notifier.h>
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#include <dsp/apr_audio-v2.h>
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#include <dsp/q6afe-v2.h>
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#include <dsp/q6core.h>
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#include <dsp/msm_mdf.h>
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@ -178,6 +179,7 @@ struct dev_config {
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u32 sample_rate;
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u32 bit_format;
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u32 channels;
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u32 data_format;
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};
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struct msm_wsa881x_dev_info {
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@ -206,6 +208,7 @@ struct msm_asoc_mach_data {
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u32 tdm_micb_voltage;
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u32 tdm_micb_current;
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bool codec_is_csra;
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void __iomem *mi2s_dsd_mode[MI2S_MAX];
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};
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struct msm_asoc_wcd93xx_codec {
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@ -478,6 +481,19 @@ static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
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static const char *const vi_feed_ch_text[] = {"One", "Two"};
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static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
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"S32_LE"};
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static const char *const data_format_text[] = {
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"LPCM",
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"Compr",
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"LPCM-60958",
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"Compr-60958",
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"NA4",
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"NA5",
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"NA6",
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"NA7",
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"NA8",
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"DSD_DOP_W_MARKER",
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"NATIVE_DSD_DATA"
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};
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static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
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"KHZ_32", "KHZ_44P1", "KHZ_48",
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"KHZ_88P2", "KHZ_96", "KHZ_176P4",
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@ -616,6 +632,8 @@ static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
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static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
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static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
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static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
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static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_data_format, data_format_text);
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static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_data_format, data_format_text);
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static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
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static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
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static SOC_ENUM_SINGLE_EXT_DECL(prim_meta_mi2s_rx_sample_rate, mi2s_rate_text);
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@ -3251,7 +3269,8 @@ static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
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return idx;
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/* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
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if ((PRIM_MI2S == idx) && (true==pdata->codec_is_csra))
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if ((idx == PRIM_MI2S) && (pdata->codec_is_csra == true)
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&& mi2s_rx_cfg[idx].data_format != AFE_DSD_DATA)
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{
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mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
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pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
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@ -3305,6 +3324,74 @@ static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
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return 0;
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}
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static int msm_mi2s_tx_data_format_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int idx = mi2s_get_port_idx(kcontrol);
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if (idx < 0)
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return idx;
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mi2s_tx_cfg[idx].data_format = ucontrol->value.enumerated.item[0];
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pr_debug("%s: idx[%d]_data_format = %d, item = %d\n", __func__,
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idx, mi2s_tx_cfg[idx].data_format,
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ucontrol->value.enumerated.item[0]);
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return 0;
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}
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static int msm_mi2s_rx_data_format_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int idx = mi2s_get_port_idx(kcontrol);
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if (idx < 0)
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return idx;
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mi2s_rx_cfg[idx].data_format = ucontrol->value.enumerated.item[0];
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pr_debug("%s: idx[%d]_data_format = %d, item = %d\n", __func__,
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idx, mi2s_rx_cfg[idx].data_format,
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ucontrol->value.enumerated.item[0]);
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return 0;
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}
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static int msm_mi2s_tx_data_format_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int idx = mi2s_get_port_idx(kcontrol);
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if (idx < 0)
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return idx;
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ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].data_format;
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pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
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idx, mi2s_tx_cfg[idx].data_format,
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ucontrol->value.enumerated.item[0]);
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return 0;
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}
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static int msm_mi2s_rx_data_format_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int idx = mi2s_get_port_idx(kcontrol);
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if (idx < 0)
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return idx;
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ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].data_format;
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pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
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idx, mi2s_rx_cfg[idx].data_format,
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ucontrol->value.enumerated.item[0]);
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return 0;
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}
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static int msm_meta_mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
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{
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int idx = 0;
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@ -4335,6 +4422,18 @@ static const struct snd_kcontrol_new msm_snd_controls[] = {
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msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
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SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
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msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
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SOC_ENUM_EXT("PRIM_MI2S_TX DataFormat", mi2s_tx_data_format,
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msm_mi2s_tx_data_format_get,
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msm_mi2s_tx_data_format_put),
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SOC_ENUM_EXT("QUAT_MI2S_TX DataFormat", mi2s_tx_data_format,
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msm_mi2s_tx_data_format_get,
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msm_mi2s_tx_data_format_put),
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SOC_ENUM_EXT("PRIM_MI2S_RX DataFormat", mi2s_rx_data_format,
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msm_mi2s_rx_data_format_get,
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msm_mi2s_rx_data_format_put),
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SOC_ENUM_EXT("QUAT_MI2S_RX DataFormat", mi2s_rx_data_format,
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msm_mi2s_rx_data_format_get,
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msm_mi2s_rx_data_format_put),
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SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
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msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
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SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
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@ -6349,7 +6448,7 @@ static struct snd_soc_ops msm_fe_qos_ops = {
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static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
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{
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int ret = 0;
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int ret = 0, val = 0;
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
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struct snd_soc_dai_link *dai_link = rtd->dai_link;
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@ -6357,6 +6456,12 @@ static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
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unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
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struct snd_soc_card *card = rtd->card;
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struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
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int data_format;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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data_format = mi2s_rx_cfg[index].data_format;
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else
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data_format = mi2s_tx_cfg[index].data_format;
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dev_dbg(rtd->card->dev,
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"%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
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@ -6382,6 +6487,9 @@ static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
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mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
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fmt = SND_SOC_DAIFMT_CBM_CFM;
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}
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if (data_format == AFE_DSD_DATA)
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fmt = SND_SOC_DAIFMT_CBM_CFS;
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ret = msm_mi2s_set_sclk(substream, true);
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if (ret < 0) {
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dev_err(rtd->card->dev,
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@ -6396,9 +6504,34 @@ static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
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__func__, index, ret);
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goto clk_off;
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}
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if (pdata->mi2s_gpio_p[index])
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msm_cdc_pinctrl_select_active_state(
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if (pdata->mi2s_gpio_p[index]) {
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if ((data_format == AFE_DSD_DATA) &&
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((index == QUAT_MI2S) ||
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(index == PRIM_MI2S))) {
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msm_cdc_pinctrl_select_alt_active_state(
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pdata->mi2s_gpio_p[index]);
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} else {
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msm_cdc_pinctrl_select_active_state(
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pdata->mi2s_gpio_p[index]);
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}
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}
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if (index == QUAT_MI2S || index == PRIM_MI2S) {
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switch (data_format) {
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case AFE_DSD_DATA:
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if (pdata->mi2s_dsd_mode[index]) {
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val = ioread32(
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pdata->mi2s_dsd_mode[index]);
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val = val | 0x1;
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iowrite32(val,
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pdata->mi2s_dsd_mode[index]);
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}
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break;
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default:
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break;
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}
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}
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}
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ret = qcs405_send_island_vad_config(dai_link->id);
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@ -6452,11 +6585,18 @@ static int msm_mi2s_snd_hw_free(struct snd_pcm_substream *substream)
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static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
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{
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int ret;
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int val;
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int data_format;
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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int index = rtd->cpu_dai->id;
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struct snd_soc_card *card = rtd->card;
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struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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data_format = mi2s_rx_cfg[index].data_format;
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else
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data_format = mi2s_tx_cfg[index].data_format;
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pr_debug("%s(): substream = %s stream = %d\n", __func__,
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substream->name, substream->stream);
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if (index < PRIM_MI2S || index >= MI2S_MAX) {
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@ -6470,6 +6610,22 @@ static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
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msm_cdc_pinctrl_select_sleep_state(
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pdata->mi2s_gpio_p[index]);
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if (index == QUAT_MI2S || index == PRIM_MI2S) {
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switch (data_format) {
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case AFE_DSD_DATA:
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if (pdata->mi2s_dsd_mode[index]) {
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val = ioread32(
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pdata->mi2s_dsd_mode[index]);
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val = val & ~1;
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iowrite32(val,
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pdata->mi2s_dsd_mode[index]);
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}
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break;
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default:
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break;
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}
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}
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ret = msm_mi2s_set_sclk(substream, false);
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if (ret < 0)
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pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
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@ -9750,6 +9906,7 @@ static int msm_asoc_machine_probe(struct platform_device *pdev)
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const char *micb_supply_str1 = "tdm-vdd-micb";
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const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
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const char *micb_current_str = "qcom,tdm-vdd-micb-current";
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u32 v_base_addr;
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if (!pdev->dev.of_node) {
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dev_err(&pdev->dev, "No platform supplied from device tree\n");
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@ -9761,6 +9918,31 @@ static int msm_asoc_machine_probe(struct platform_device *pdev)
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if (!pdata)
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return -ENOMEM;
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ret = of_property_read_u32(
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pdev->dev.of_node, "tcsr_i2s_dsd_prim", &v_base_addr);
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if (ret) {
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dev_err(&pdev->dev, "MUX addr invalid for MI2S dsd prim\n");
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} else {
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pdata->mi2s_dsd_mode[PRIM_MI2S] =
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devm_ioremap(&pdev->dev, v_base_addr, 4);
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if (pdata->mi2s_dsd_mode[PRIM_MI2S] == NULL) {
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pr_err("%s ioremap failure for muxsel virt addr dsd prim\n",
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__func__);
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}
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}
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ret = of_property_read_u32(
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pdev->dev.of_node, "tcsr_i2s_dsd_quat", &v_base_addr);
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if (ret) {
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dev_err(&pdev->dev, "MUX addr invalid for MI2S dsd quat\n");
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} else {
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pdata->mi2s_dsd_mode[QUAT_MI2S] =
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devm_ioremap(&pdev->dev, v_base_addr, 4);
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if (pdata->mi2s_dsd_mode[QUAT_MI2S] == NULL) {
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pr_err("%s ioremap failure for muxsel virt addr dsd quat\n",
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__func__);
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}
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}
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/* test for ep92 HDMI bridge and update dai links accordingly */
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ret = msm_detect_ep92_dev(pdev, card);
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if (ret)
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