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Samsung DTS ARM changes for v4.21

Browse source 
1. Add missing properties and nodes for PMIC clocks in multiple DTS
    files.
 2. Add UHS-I bus speed support to Odroid XU3/XU4/HC SD card and bump the
    maximum clock frequency to 200 MHz for SD and eMMC.
 3. Update cooling maps to include all CPU devices in multiple DTS files.
 4. Enable quirks for Exynos3250 DWC.
 5. Add JPEG CODEC node to S5Pv210.
 6. Add opp-suspend to devfreq OPPs on Exynos4 boards to fix resuming
    from suspend to RAM.
 7. Remove eDP from Arndale board as it does not work and breaks also
    DSI.
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Merge tag 'samsung-dt-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Samsung DTS ARM changes for v4.21

1. Add missing properties and nodes for PMIC clocks in multiple DTS
   files.
2. Add UHS-I bus speed support to Odroid XU3/XU4/HC SD card and bump the
   maximum clock frequency to 200 MHz for SD and eMMC.
3. Update cooling maps to include all CPU devices in multiple DTS files.
4. Enable quirks for Exynos3250 DWC.
5. Add JPEG CODEC node to S5Pv210.
6. Add opp-suspend to devfreq OPPs on Exynos4 boards to fix resuming
   from suspend to RAM.
7. Remove eDP from Arndale board as it does not work and breaks also
   DSI.

* tag 'samsung-dt-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: remove display-port node from Arndale
  ARM: dts: exynos: Add opp-suspend to DMC and leftbus devfreq OPPs on Exynos4
  ARM: dts: s5pv210: Add s5p-jpeg codec node.
  ARM: dts: exynos: Use Samsung SoC specific compatible for DWC2 module
  ARM: dts: exynos: Add all CPUs in cooling maps
  ARM: dts: exynos: Clarify comment explaining purpose of Odroid XU3 DTSI
  ARM: dts: exynos: Add pin configuration for SD write protect on Odroid XU3/XU4/HC1
  ARM: dts: exynos: Update maximum frequency for eMMC to 200MHz on Odroid XU3/XU4
  ARM: dts: exynos: Update maximum frequency for SD card to 200MHz on Odroid XU3/XU4/HC1
  ARM: dts: exynos: Fix LDO13 min values on Odroid XU3/XU4/HC1
  ARM: dts: exynos: Add UHS-I bus speed support to Odroid XU3/XU4/HC1
  ARM: dts: exynos: Add missing clocks to RTC node for Arndale board
  ARM: dts: exynos: Add compatible for s5m8767 clocks node on Itop Core
  ARM: dts: exynos: Add compatible for s2mps11 clocks node on Exynos542x

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-12-12 12:52:20 -08:00
commit df6aeaef1c
20 changed files with 221 additions and 143 deletions
Download patch file Download diff file Expand all files Collapse all files

6
arch/arm/boot/dts/exynos3250-artik5.dtsi
View file

@ -36,11 +36,13 @@
cooling-maps {
map0 {
/* Corresponds to 500MHz */
cooling-device = <&cpu0 5 5>;
cooling-device = <&cpu0 5 5>,
<&cpu1 5 5>;
};
map1 {
/* Corresponds to 200MHz */
cooling-device = <&cpu0 8 8>;
cooling-device = <&cpu0 8 8>,
<&cpu1 8 8>;
};
};
};

6
arch/arm/boot/dts/exynos3250-monk.dts
View file

@ -121,11 +121,13 @@
cooling-maps {
map0 {
/* Correspond to 500MHz at freq_table */
cooling-device = <&cpu0 5 5>;
cooling-device = <&cpu0 5 5>,
<&cpu1 5 5>;
};
map1 {
/* Correspond to 200MHz at freq_table */
cooling-device = <&cpu0 8 8>;
cooling-device = <&cpu0 8 8>,
<&cpu1 8 8>;
};
};
};

6
arch/arm/boot/dts/exynos3250-rinato.dts
View file

@ -116,11 +116,13 @@
cooling-maps {
map0 {
/* Corresponds to 500MHz */
cooling-device = <&cpu0 5 5>;
cooling-device = <&cpu0 5 5>,
<&cpu1 5 5>;
};
map1 {
/* Corresponds to 200MHz */
cooling-device = <&cpu0 8 8>;
cooling-device = <&cpu0 8 8>,
<&cpu1 8 8>;
};
};
};

2
arch/arm/boot/dts/exynos3250.dtsi
View file

@ -357,7 +357,7 @@
};
hsotg: hsotg@12480000 {
compatible = "snps,dwc2";
compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
reg = <0x12480000 0x20000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBOTG>;

4
arch/arm/boot/dts/exynos4210-trats.dts
View file

@ -138,11 +138,11 @@
cooling-maps {
map0 {
/* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 2 2>;
cooling-device = <&cpu0 2 2>, <&cpu1 2 2>;
};
map1 {
/* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 4 4>;
cooling-device = <&cpu0 4 4>, <&cpu1 4 4>;
};
};
};

4
arch/arm/boot/dts/exynos4210.dtsi
View file

@ -51,7 +51,7 @@
#cooling-cells = <2>; /* min followed by max */
};
cpu@901 {
cpu1: cpu@901 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x901>;
@ -298,6 +298,7 @@
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1150000>;
opp-suspend;
};
};
@ -367,6 +368,7 @@
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-suspend;
};
};
};

9
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
View file

@ -45,11 +45,15 @@
cooling-maps {
map0 {
/* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 7 7>;
cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
<&cpu2 7 7>, <&cpu3 7 7>;
};
map1 {
/* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 13 13>;
cooling-device = <&cpu0 13 13>,
<&cpu1 13 13>,
<&cpu2 13 13>,
<&cpu3 13 13>;
};
};
};
@ -446,6 +450,7 @@
};
s5m8767_osc: clocks {
compatible = "samsung,s5m8767-clk";
#clock-cells = <1>;
clock-output-names = "s5m8767_ap",
"s5m8767_cp", "s5m8767_bt";

8
arch/arm/boot/dts/exynos4412-midas.dtsi
View file

@ -267,11 +267,15 @@
cooling-maps {
map0 {
/* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 7 7>;
cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
<&cpu2 7 7>, <&cpu3 7 7>;
};
map1 {
/* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 13 13>;
cooling-device = <&cpu0 13 13>,
<&cpu1 13 13>,
<&cpu2 13 13>,
<&cpu3 13 13>;
};
};
};

8
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
View file

@ -72,11 +72,15 @@
cooling-maps {
cooling_map0: map0 {
/* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 7 7>;
cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
<&cpu2 7 7>, <&cpu3 7 7>;
};
cooling_map1: map1 {
/* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 13 13>;
cooling-device = <&cpu0 13 13>,
<&cpu1 13 13>,
<&cpu2 13 13>,
<&cpu3 13 13>;
};
};
};

18
arch/arm/boot/dts/exynos4412-odroidu3.dts
View file

@ -45,24 +45,22 @@
cooling-maps {
map0 {
trip = <&cpu_alert1>;
cooling-device = <&cpu0 9 9>;
cooling-device = <&cpu0 9 9>, <&cpu1 9 9>,
<&cpu2 9 9>, <&cpu3 9 9>,
<&fan0 1 2>;
};
map1 {
trip = <&cpu_alert2>;
cooling-device = <&cpu0 15 15>;
cooling-device = <&cpu0 15 15>,
<&cpu1 15 15>,
<&cpu2 15 15>,
<&cpu3 15 15>,
<&fan0 2 3>;
};
map2 {
trip = <&cpu_alert0>;
cooling-device = <&fan0 0 1>;
};
map3 {
trip = <&cpu_alert1>;
cooling-device = <&fan0 1 2>;
};
map4 {
trip = <&cpu_alert2>;
cooling-device = <&fan0 2 3>;
};
};
};
};

8
arch/arm/boot/dts/exynos4412.dtsi
View file

@ -45,7 +45,7 @@
#cooling-cells = <2>; /* min followed by max */
};
cpu@a01 {
cpu1: cpu@a01 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA01>;
@ -55,7 +55,7 @@
#cooling-cells = <2>; /* min followed by max */
};
cpu@a02 {
cpu2: cpu@a02 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA02>;
@ -65,7 +65,7 @@
#cooling-cells = <2>; /* min followed by max */
};
cpu@a03 {
cpu3: cpu@a03 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA03>;
@ -432,6 +432,7 @@
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1050000>;
opp-suspend;
};
};
@ -520,6 +521,7 @@
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1000000>;
opp-suspend;
};
};

34
arch/arm/boot/dts/exynos5250-arndale.dts
View file

@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/samsung,s2mps11.h>
#include "exynos5250.dtsi"
/ {
@ -180,31 +181,6 @@
};
};
&dp {
status = "okay";
samsung,color-space = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
display-timings {
native-mode = <&timing0>;
timing0: timing {
/* 2560x1600 DP panel */
clock-frequency = <50000>;
hactive = <2560>;
vactive = <1600>;
hfront-porch = <48>;
hback-porch = <80>;
hsync-len = <32>;
vback-porch = <16>;
vfront-porch = <8>;
vsync-len = <6>;
};
};
};
&fimd {
status = "okay";
};
@ -264,6 +240,12 @@
<&gpx2 4 GPIO_ACTIVE_HIGH>,
<&gpx2 5 GPIO_ACTIVE_HIGH>;
s5m8767_osc: clocks {
compatible = "samsung,s5m8767-clk";
#clock-cells = <1>;
clock-output-names = "s5m8767_ap", "unused1", "unused2";
};
regulators {
ldo1_reg: LDO1 {
regulator-name = "VDD_ALIVE_1.0V";
@ -601,6 +583,8 @@
};
&rtc {
clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
clock-names = "rtc", "rtc_src";
status = "okay";
};

7
arch/arm/boot/dts/exynos5250.dtsi
View file

@ -59,7 +59,7 @@
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
@ -1087,11 +1087,12 @@
cooling-maps {
map0 {
/* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 9 9>;
cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
};
map1 {
/* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 15 15>;
cooling-device = <&cpu0 15 15>,
<&cpu1 15 15>;
};
};
};

1
arch/arm/boot/dts/exynos5420-arndale-octa.dts
View file

@ -89,6 +89,7 @@
pinctrl-0 = <&s2mps11_irq>;
s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
#clock-cells = <1>;
clock-output-names = "s2mps11_ap",
"s2mps11_cp", "s2mps11_bt";

7
arch/arm/boot/dts/exynos5420-pinctrl.dtsi
View file

@ -289,6 +289,13 @@
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd2_wp: sd2-wp {
samsung,pins = "gpc4-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
};
&pinctrl_2 {

1
arch/arm/boot/dts/exynos5420-smdk5420.dts
View file

@ -141,6 +141,7 @@
reg = <0x66>;
s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
#clock-cells = <1>;
clock-output-names = "s2mps11_ap",
"s2mps11_cp", "s2mps11_bt";

11
arch/arm/boot/dts/exynos5422-odroid-core.dtsi
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Hardkernel Odroid XU3/XU4/HC1 boards core device tree source
* Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
*
* Copyright (c) 2017 Marek Szyprowski
* Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
@ -141,6 +141,7 @@
pinctrl-0 = <&s2mps11_irq>;
s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
#clock-cells = <1>;
clock-output-names = "s2mps11_ap",
"s2mps11_cp", "s2mps11_bt";
@ -231,7 +232,7 @@
ldo13_reg: LDO13 {
regulator-name = "vddq_mmc2";
regulator-min-microvolt = <2800000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
};
@ -498,11 +499,15 @@
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <200000000>;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
sd-uhs-sdr50;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&nocp_mem0_0 {

106
arch/arm/boot/dts/exynos5422-odroidhc1.dts
View file

@ -56,24 +56,30 @@
*/
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&cpu0 0 2>;
};
map1 {
trip = <&cpu0_alert0>;
cooling-device = <&cpu4 0 2>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
/*
* When reaching cpu0_alert1, reduce CPU
* further, down to 600 MHz (12 steps for big,
* 7 steps for LITTLE).
*/
map2 {
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&cpu0 3 7>;
};
map3 {
trip = <&cpu0_alert1>;
cooling-device = <&cpu4 3 12>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
};
};
@ -99,19 +105,25 @@
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&cpu0 0 2>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map1 {
trip = <&cpu1_alert0>;
cooling-device = <&cpu4 0 2>;
};
map2 {
trip = <&cpu1_alert1>;
cooling-device = <&cpu0 3 7>;
};
map3 {
trip = <&cpu1_alert1>;
cooling-device = <&cpu4 3 12>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
};
};
@ -137,19 +149,25 @@
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&cpu0 0 2>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map1 {
trip = <&cpu2_alert0>;
cooling-device = <&cpu4 0 2>;
};
map2 {
trip = <&cpu2_alert1>;
cooling-device = <&cpu0 3 7>;
};
map3 {
trip = <&cpu2_alert1>;
cooling-device = <&cpu4 3 12>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
};
};
@ -175,19 +193,25 @@
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&cpu0 0 2>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map1 {
trip = <&cpu3_alert0>;
cooling-device = <&cpu4 0 2>;
};
map2 {
trip = <&cpu3_alert1>;
cooling-device = <&cpu0 3 7>;
};
map3 {
trip = <&cpu3_alert1>;
cooling-device = <&cpu4 3 12>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
};
};

109
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Hardkernel Odroid XU3 board device tree source
* Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@ -113,24 +113,30 @@
*/
map3 {
trip = <&cpu0_alert3>;
cooling-device = <&cpu0 0 2>;
};
map4 {
trip = <&cpu0_alert3>;
cooling-device = <&cpu4 0 2>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
/*
* When reaching cpu0_alert4, reduce CPU
* further, down to 600 MHz (12 steps for big,
* 7 steps for LITTLE).
*/
map5 {
map4 {
trip = <&cpu0_alert4>;
cooling-device = <&cpu0 3 7>;
};
map6 {
trip = <&cpu0_alert4>;
cooling-device = <&cpu4 3 12>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
};
};
@ -185,19 +191,25 @@
};
map3 {
trip = <&cpu1_alert3>;
cooling-device = <&cpu0 0 2>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
trip = <&cpu1_alert3>;
cooling-device = <&cpu4 0 2>;
};
map5 {
trip = <&cpu1_alert4>;
cooling-device = <&cpu0 3 7>;
};
map6 {
trip = <&cpu1_alert4>;
cooling-device = <&cpu4 3 12>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
};
};
@ -252,19 +264,25 @@
};
map3 {
trip = <&cpu2_alert3>;
cooling-device = <&cpu0 0 2>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
trip = <&cpu2_alert3>;
cooling-device = <&cpu4 0 2>;
};
map5 {
trip = <&cpu2_alert4>;
cooling-device = <&cpu0 3 7>;
};
map6 {
trip = <&cpu2_alert4>;
cooling-device = <&cpu4 3 12>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
};
};
@ -319,19 +337,25 @@
};
map3 {
trip = <&cpu3_alert3>;
cooling-device = <&cpu0 0 2>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
trip = <&cpu3_alert3>;
cooling-device = <&cpu4 0 2>;
};
map5 {
trip = <&cpu3_alert4>;
cooling-device = <&cpu0 3 7>;
};
map6 {
trip = <&cpu3_alert4>;
cooling-device = <&cpu4 3 12>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
};
};
@ -392,6 +416,7 @@
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
max-frequency = <200000000>;
vmmc-supply = <&ldo18_reg>;
vqmmc-supply = <&ldo3_reg>;
};

9
arch/arm/boot/dts/s5pv210.dtsi
View file

@ -627,6 +627,15 @@
samsung,lcd-wb;
};
};
jpeg_codec: jpeg-codec@fb600000 {
compatible = "samsung,s5pv210-jpeg";
reg = <0xfb600000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <8>;
clocks = <&clocks CLK_JPEG>;
clock-names = "jpeg";
};
};
};