mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-26 06:33:19 -04:00
Merge branch 'drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (53 commits) drm: detect hdmi monitor by hdmi identifier (v3) drm: drm_fops.c unlock missing on error path drm: reorder struct drm_ioctl_desc to save space on 64 bit builds radeon: add some new pci ids drm: read EDID extensions from monitor drm: Use a little stash on the stack to avoid kmalloc in most DRM ioctls. drm/radeon: add regs required for occlusion queries support drm/i915: check the return value from the copy from user drm/radeon: fix logic in r600_page_table_init() to match ati_gart drm/radeon: r600 ptes are 64-bit, cleanup cleanup function. drm/radeon: don't call irq changes on r600 suspend/resume drm/radeon: fix r600 writeback across suspend/resume drm/radeon: fix r600 writeback setup. drm: fix warnings about new mappings in info code. drm/radeon: NULL noise: drivers/gpu/drm/radeon/radeon_*.c drm/radeon: fix r600 pci mapping calls. drm/radeon: r6xx/r7xx: fix possible oops in r600_page_table_cleanup() radeon: call the correct idle function, logic got inverted. drm/radeon: RS600: fix interrupt handling drm/r600: fix rptr address along lines of previous fixes to radeon. ...
This commit is contained in:
Linus Torvalds
commit
dfbbe89e19
39 changed files with 27309 additions and 434 deletions
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@ -281,16 +281,16 @@ typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd,
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struct drm_ioctl_desc {
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unsigned int cmd;
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drm_ioctl_t *func;
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int flags;
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drm_ioctl_t *func;
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};
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/**
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* Creates a driver or general drm_ioctl_desc array entry for the given
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* ioctl, for use by drm_ioctl().
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*/
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#define DRM_IOCTL_DEF(ioctl, func, flags) \
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[DRM_IOCTL_NR(ioctl)] = {ioctl, func, flags}
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#define DRM_IOCTL_DEF(ioctl, _func, _flags) \
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[DRM_IOCTL_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags}
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struct drm_magic_entry {
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struct list_head head;
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@ -522,20 +522,33 @@ struct drm_mm {
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};
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/**
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* Kernel side of a mapping
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*/
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struct drm_local_map {
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resource_size_t offset; /**< Requested physical address (0 for SAREA)*/
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unsigned long size; /**< Requested physical size (bytes) */
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enum drm_map_type type; /**< Type of memory to map */
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enum drm_map_flags flags; /**< Flags */
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void *handle; /**< User-space: "Handle" to pass to mmap() */
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/**< Kernel-space: kernel-virtual address */
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int mtrr; /**< MTRR slot used */
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};
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typedef struct drm_local_map drm_local_map_t;
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/**
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* Mappings list
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*/
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struct drm_map_list {
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struct list_head head; /**< list head */
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struct drm_hash_item hash;
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struct drm_map *map; /**< mapping */
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struct drm_local_map *map; /**< mapping */
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uint64_t user_token;
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struct drm_master *master;
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struct drm_mm_node *file_offset_node; /**< fake offset */
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};
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typedef struct drm_map drm_local_map_t;
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/**
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* Context handle list
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*/
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@ -560,7 +573,7 @@ struct drm_ati_pcigart_info {
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dma_addr_t bus_addr;
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dma_addr_t table_mask;
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struct drm_dma_handle *table_handle;
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drm_local_map_t mapping;
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struct drm_local_map mapping;
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int table_size;
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};
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@ -675,7 +688,6 @@ struct drm_driver {
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int (*kernel_context_switch) (struct drm_device *dev, int old,
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int new);
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void (*kernel_context_switch_unlock) (struct drm_device *dev);
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int (*dri_library_name) (struct drm_device *dev, char *buf);
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/**
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* get_vblank_counter - get raw hardware vblank counter
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@ -747,8 +759,8 @@ struct drm_driver {
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struct drm_file *file_priv);
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void (*reclaim_buffers_idlelocked) (struct drm_device *dev,
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struct drm_file *file_priv);
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unsigned long (*get_map_ofs) (struct drm_map * map);
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unsigned long (*get_reg_ofs) (struct drm_device *dev);
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resource_size_t (*get_map_ofs) (struct drm_local_map * map);
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resource_size_t (*get_reg_ofs) (struct drm_device *dev);
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void (*set_version) (struct drm_device *dev,
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struct drm_set_version *sv);
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@ -981,7 +993,7 @@ struct drm_device {
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sigset_t sigmask;
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struct drm_driver *driver;
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drm_local_map_t *agp_buffer_map;
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struct drm_local_map *agp_buffer_map;
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unsigned int agp_buffer_token;
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struct drm_minor *control; /**< Control node for card */
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struct drm_minor *primary; /**< render type primary screen head */
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@ -1098,8 +1110,8 @@ extern int drm_release(struct inode *inode, struct file *filp);
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extern int drm_mmap(struct file *filp, struct vm_area_struct *vma);
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extern int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma);
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extern void drm_vm_open_locked(struct vm_area_struct *vma);
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extern unsigned long drm_core_get_map_ofs(struct drm_map * map);
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extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev);
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extern resource_size_t drm_core_get_map_ofs(struct drm_local_map * map);
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extern resource_size_t drm_core_get_reg_ofs(struct drm_device *dev);
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extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait);
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/* Memory management support (drm_memory.h) */
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@ -1202,13 +1214,13 @@ extern int drm_i_have_hw_lock(struct drm_device *dev, struct drm_file *file_priv
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/* Buffer management support (drm_bufs.h) */
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extern int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc * request);
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extern int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc * request);
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extern int drm_addmap(struct drm_device *dev, unsigned int offset,
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extern int drm_addmap(struct drm_device *dev, resource_size_t offset,
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unsigned int size, enum drm_map_type type,
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enum drm_map_flags flags, drm_local_map_t ** map_ptr);
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enum drm_map_flags flags, struct drm_local_map **map_ptr);
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extern int drm_addmap_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int drm_rmmap(struct drm_device *dev, drm_local_map_t *map);
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extern int drm_rmmap_locked(struct drm_device *dev, drm_local_map_t *map);
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extern int drm_rmmap(struct drm_device *dev, struct drm_local_map *map);
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extern int drm_rmmap_locked(struct drm_device *dev, struct drm_local_map *map);
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extern int drm_rmmap_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int drm_addbufs(struct drm_device *dev, void *data,
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@ -1222,10 +1234,10 @@ extern int drm_freebufs(struct drm_device *dev, void *data,
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extern int drm_mapbufs(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int drm_order(unsigned long size);
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extern unsigned long drm_get_resource_start(struct drm_device *dev,
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extern resource_size_t drm_get_resource_start(struct drm_device *dev,
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unsigned int resource);
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extern resource_size_t drm_get_resource_len(struct drm_device *dev,
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unsigned int resource);
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extern unsigned long drm_get_resource_len(struct drm_device *dev,
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unsigned int resource);
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/* DMA support (drm_dma.h) */
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extern int drm_dma_setup(struct drm_device *dev);
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@ -1301,7 +1313,7 @@ extern struct drm_master *drm_master_get(struct drm_master *master);
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extern void drm_master_put(struct drm_master **master);
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extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
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struct drm_driver *driver);
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extern int drm_put_dev(struct drm_device *dev);
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extern void drm_put_dev(struct drm_device *dev);
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extern int drm_put_minor(struct drm_minor **minor);
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extern unsigned int drm_debug;
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@ -1311,7 +1323,7 @@ extern struct dentry *drm_debugfs_root;
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extern struct idr drm_minors_idr;
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extern drm_local_map_t *drm_getsarea(struct drm_device *dev);
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extern struct drm_local_map *drm_getsarea(struct drm_device *dev);
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/* Proc support (drm_proc.h) */
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extern int drm_proc_init(struct drm_minor *minor, int minor_id,
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@ -1453,12 +1465,12 @@ int drm_gem_open_ioctl(struct drm_device *dev, void *data,
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void drm_gem_open(struct drm_device *dev, struct drm_file *file_private);
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void drm_gem_release(struct drm_device *dev, struct drm_file *file_private);
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extern void drm_core_ioremap(struct drm_map *map, struct drm_device *dev);
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extern void drm_core_ioremap_wc(struct drm_map *map, struct drm_device *dev);
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extern void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev);
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extern void drm_core_ioremap(struct drm_local_map *map, struct drm_device *dev);
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extern void drm_core_ioremap_wc(struct drm_local_map *map, struct drm_device *dev);
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extern void drm_core_ioremapfree(struct drm_local_map *map, struct drm_device *dev);
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static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev,
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unsigned int token)
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static __inline__ struct drm_local_map *drm_core_findmap(struct drm_device *dev,
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unsigned int token)
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{
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struct drm_map_list *_entry;
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list_for_each_entry(_entry, &dev->maplist, head)
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@ -1485,7 +1497,7 @@ static __inline__ int drm_device_is_pcie(struct drm_device *dev)
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return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP);
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}
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static __inline__ void drm_core_dropmap(struct drm_map *map)
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static __inline__ void drm_core_dropmap(struct drm_local_map *map)
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{
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}
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@ -550,7 +550,7 @@ struct drm_mode_config {
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int min_width, min_height;
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int max_width, max_height;
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struct drm_mode_config_funcs *funcs;
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unsigned long fb_base;
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resource_size_t fb_base;
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/* pointers to standard properties */
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struct list_head property_blob_list;
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@ -613,7 +613,8 @@ extern void drm_fb_release(struct drm_file *file_priv);
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extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group);
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extern struct edid *drm_get_edid(struct drm_connector *connector,
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struct i2c_adapter *adapter);
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extern unsigned char *drm_do_probe_ddc_edid(struct i2c_adapter *adapter);
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extern int drm_do_probe_ddc_edid(struct i2c_adapter *adapter,
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unsigned char *buf, int len);
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extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
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extern void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode);
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extern void drm_mode_remove(struct drm_connector *connector, struct drm_display_mode *mode);
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@ -731,4 +732,5 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev,
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void *data, struct drm_file *file_priv);
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extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
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void *data, struct drm_file *file_priv);
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extern bool drm_detect_hdmi_monitor(struct edid *edid);
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#endif /* __DRM_CRTC_H__ */
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@ -6,6 +6,19 @@
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#include <linux/interrupt.h> /* For task queue support */
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#include <linux/delay.h>
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#ifndef readq
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static u64 readq(void __iomem *reg)
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{
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return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
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}
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static void writeq(u64 val, void __iomem *reg)
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{
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writel(val & 0xffffffff, reg);
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writel(val >> 32, reg + 0x4UL);
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}
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#endif
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/** Current process ID */
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#define DRM_CURRENTPID task_pid_nr(current)
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#define DRM_SUSER(p) capable(CAP_SYS_ADMIN)
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@ -23,6 +36,12 @@
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/** Write a dword into a MMIO region */
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#define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset))
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/** Read memory barrier */
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/** Read a qword from a MMIO region - be careful using these unless you really understand them */
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#define DRM_READ64(map, offset) readq(((void __iomem *)(map)->handle) + (offset))
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/** Write a qword into a MMIO region */
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#define DRM_WRITE64(map, offset, val) writeq(val, ((void __iomem *)(map)->handle) + (offset))
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#define DRM_READMEMORYBARRIER() rmb()
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/** Write memory barrier */
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#define DRM_WRITEMEMORYBARRIER() wmb()
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@ -239,10 +239,123 @@
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{0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
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{0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
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{0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
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{0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
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{0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
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{0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
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{0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
|
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{0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
|
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{0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
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{0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
|
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{0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
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||||
{0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0, 0, 0}
|
||||
|
||||
#define r128_PCI_IDS \
|
||||
|
|
|
|||
|
|
@ -306,6 +306,8 @@ typedef union {
|
|||
|
||||
#define RADEON_SCRATCH_REG_OFFSET 32
|
||||
|
||||
#define R600_SCRATCH_REG_OFFSET 256
|
||||
|
||||
#define RADEON_NR_SAREA_CLIPRECTS 12
|
||||
|
||||
/* There are 2 heaps (local/GART). Each region within a heap is a
|
||||
|
|
@ -528,7 +530,8 @@ typedef struct drm_radeon_init {
|
|||
RADEON_INIT_CP = 0x01,
|
||||
RADEON_CLEANUP_CP = 0x02,
|
||||
RADEON_INIT_R200_CP = 0x03,
|
||||
RADEON_INIT_R300_CP = 0x04
|
||||
RADEON_INIT_R300_CP = 0x04,
|
||||
RADEON_INIT_R600_CP = 0x05
|
||||
} func;
|
||||
unsigned long sarea_priv_offset;
|
||||
int is_pci;
|
||||
|
|
|
|||
Loading…
Reference in a new issue