From 5f1ea1aa0cf1345c8cd09a4c5a94fd2b0cc45e8c Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Wed, 17 Feb 2021 10:21:29 +0530 Subject: [PATCH] iommu/arm-smmu: update debug logs for qsmmuv2 sync timeout Add debug registers to dump in the event of sync timeout for qsmmuv2. Change-Id: I18cc3296e74ca0e2cb6f68f8aca67032d493410b Signed-off-by: Prakash Gupta --- drivers/iommu/arm-smmu-qcom.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index d606a7de8e78..b2199a484a91 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #include @@ -20,6 +20,8 @@ #include #define IMPL_DEF4_MICRO_MMU_CTRL 0 +#define IMPL_DEF4_CLK_ON_STATUS 0x50 +#define IMPL_DEF4_CLK_ON_CLIENT_STATUS 0x54 #define MICRO_MMU_CTRL_LOCAL_HALT_REQ BIT(2) #define MICRO_MMU_CTRL_IDLE BIT(3) @@ -193,8 +195,17 @@ static phys_addr_t qsmmuv2_iova_to_phys_hard( static void qsmmuv2_tlb_sync_timeout(struct arm_smmu_device *smmu) { + u32 clk_on, clk_on_client; + dev_err_ratelimited(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n"); + clk_on = arm_smmu_readl(smmu, ARM_SMMU_IMPL_DEF4, + IMPL_DEF4_CLK_ON_STATUS); + clk_on_client = arm_smmu_readl(smmu, ARM_SMMU_IMPL_DEF4, + IMPL_DEF4_CLK_ON_CLIENT_STATUS); + dev_err_ratelimited(smmu->dev, + "clk on 0x%x, clk on client 0x%x status\n", + clk_on, clk_on_client); BUG_ON(IS_ENABLED(CONFIG_IOMMU_TLBSYNC_DEBUG)); }