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msm: kgsl: Override UBWC configuration for A660 based on DDR type

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The highest bank bit defined in the A660 gpucore structure defaults
to DDR type 8. If underlying DDR is type 7, then modify the highest
bank bit accordingly.

Change-Id: Idd36f69227dca63eef19c1ac1843b88982346edd
Signed-off-by: Raghu Ananya Arabolu <rarabolu@codeaurora.org>
This commit is contained in:
Raghu Ananya Arabolu 2020-01-23 11:12:12 -08:00
commit dfdd7d2890
1 changed files with 3 additions and 1 deletions
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4
drivers/gpu/msm/adreno_a6xx.c
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@ -106,7 +106,9 @@ static void a6xx_init(struct adreno_device *adreno_dev)
adreno_dev->highest_bank_bit = a6xx_core->highest_bank_bit;
if (adreno_is_a650(adreno_dev) && of_fdt_get_ddrtype() == 0x7)
/* If the memory type is DDR 4, override the existing configuration */
if ((adreno_is_a650(adreno_dev) || adreno_is_a660(adreno_dev)) &&
of_fdt_get_ddrtype() == 0x7)
adreno_dev->highest_bank_bit = 15;
a6xx_crashdump_init(adreno_dev);