From e0440bc50233d8534d504defcf2f2cb4e404a92c Mon Sep 17 00:00:00 2001 From: Priyadarshnee S Date: Fri, 6 Sep 2019 12:25:50 +0530 Subject: [PATCH] qcacmn: Find proper radar-found secondary frequency when preCAC is running Bring up a Hawkeye AP in ETSI domain in HT80_80 mode and enable preCAC (preCACEn). When preCAC timer is running, if radar gets detected in the secondary segment (which is DFS), dfs_get_bonding_channels() gets invoked to find the radar affected channels's IEEE. The radar-found channel's IEEE gets computed from "dfs_precac_secondary_freq" variable which does not get populated for Lithium chipsets as "dfs_precac_secondary_freq" is specific to legacy preCAC. Since the secondary 80 channel's IEEE gets assigned as 0, radar-found frequency gets computed wrongly and channels are not added to NOL. Ensure that "dfs_precac_secondary_freq" is used for secondary frequency computation only for legacy chips. For chips that have a separate agile radar detector engine, use "dfs_ch_vhtop_ch_freq_seg2" variable to compute the secondary frequency. CRs-Fixed: 2521686 Change-Id: I50e1c496ce81d532408d61d21bac568c8d755b2c --- .../core/src/misc/dfs_process_radar_found_ind.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/umac/dfs/core/src/misc/dfs_process_radar_found_ind.c b/umac/dfs/core/src/misc/dfs_process_radar_found_ind.c index fd549ff4b8ba..9e4af40c8a27 100644 --- a/umac/dfs/core/src/misc/dfs_process_radar_found_ind.c +++ b/umac/dfs/core/src/misc/dfs_process_radar_found_ind.c @@ -530,9 +530,19 @@ uint8_t dfs_get_bonding_channels(struct wlan_dfs *dfs, else { /* When precac is running "dfs_ch_vhtop_ch_freq_seg2" is * zero and "dfs_precac_secondary_freq" holds the secondary - * frequency. + * frequency in case of legacy chips. + * For chips that support a separate agile detector engine, + * "dfs_agile_precac_freq" holds the frequency that agile + * engine operates on. + * + * In case of radar detected by the HW in the secondary 80 + * channel,"dfs_ch_vhtop_ch_freq_seg2" holds the secondary + * segment center frequency in the below cases: + * 1. preCAC timer is running in chips that support separate + * agile engines. + * 2. preCAC timer is not running. */ - if (dfs_is_precac_timer_running(dfs)) + if (dfs_is_precac_timer_running(dfs) && dfs->dfs_precac_enable) center_chan = dfs->dfs_precac_secondary_freq; else center_chan = curchan->dfs_ch_vhtop_ch_freq_seg2;