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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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pci: switch: Add snapshot of PCIe switch driver
Add snapshot for switch driver stack from msm-4.14.c4 commit
ad8af976b4ab6 ("regulator: qpnp-lcdb: Disable step voltage ramp
for PM8150L V3").
Change-Id: I184823baa47f21c93e8bd6cc60c17fe790b92cfa
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
This commit is contained in:
Hemant Kumar
parent
73db1046f1
commit
e056332148
3 changed files with 317 additions and 0 deletions
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@ -12,4 +12,13 @@ config PCI_SW_SWITCHTEC
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devices. See <file:Documentation/driver-api/switchtec.rst> for more
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information.
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config PCI_SW_QCOM_SWITCH
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depends on ARCH_QCOM
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tristate "Qualcomm Technologies, Inc. PCIe Switch Management Driver"
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help
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Enables support for switches connected to Qualcomm Technologies, Inc.
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PCIe Rootport. Switches that require erratas can bind with this driver
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and run errata for the corresponding port. Values can be saved and
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restored using this driver during suspend and resume.
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endmenu
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@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PCI_SW_SWITCHTEC) += switchtec.o
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obj-$(CONFIG_PCI_SW_QCOM_SWITCH) += switch-qcom.o
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307
drivers/pci/switch/switch-qcom.c
Normal file
307
drivers/pci/switch/switch-qcom.c
Normal file
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@ -0,0 +1,307 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */
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/*
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* MSM PCIe switch controller
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*/
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <linux/of.h>
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#define DIODE_VENDOR_ID 0x12d8
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#define DIODE_DEVICE_ID 0xb304
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/*
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* @DIODE_ERRATA_0: Apply errata specific to the upstream port (USP).
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* @DIODE_ERRATA_1: Apply errata configuration to downstream port1 (DSP1).
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* @DIODE_ERRATA_2: Common errata applied to (DSP2) port in the switch.
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*/
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enum {
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DIODE_ERRATA_0,
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DIODE_ERRATA_1,
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DIODE_ERRATA_2,
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SWITCH_MAX,
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};
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struct pci_qcom_switch_errata {
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int (*config_errata)(struct device *dev, void *data);
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};
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/*
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* Supports configuring Port Arbitration for VC0 only. Also,
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* current support is only dword updates for parb_phase_value.
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*/
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static int config_port_arbitration(struct device *dev, int parb_select,
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u32 parb_phase_value)
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{
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struct pci_dev *pcidev = to_pci_dev(dev);
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int i, pos, size;
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int timeout = 100;
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u32 parb_offset, parb_phase, parb_size;
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u32 val;
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u16 status;
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pos = pci_find_ext_capability(pcidev, PCI_EXT_CAP_ID_VC);
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if (!pos) {
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pr_err("port %s: could not find VC capability register\n");
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return -EIO;
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}
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pci_read_config_dword(pcidev, pos + PCI_VC_RES_CAP, &val);
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parb_offset = ((val & PCI_VC_RES_CAP_ARB_OFF) >> 24) * 16;
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if (val & PCI_VC_RES_CAP_256_PHASE)
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parb_phase = 256;
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else if (val & (PCI_VC_RES_CAP_128_PHASE |
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PCI_VC_RES_CAP_128_PHASE_TB))
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parb_phase = 128;
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else if (val & PCI_VC_RES_CAP_64_PHASE)
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parb_phase = 64;
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else if (val & PCI_VC_RES_CAP_32_PHASE)
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parb_phase = 32;
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pci_read_config_dword(pcidev, pos + PCI_VC_PORT_CAP1, &val);
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/* Port Arbitration Table Entry Size (bits) */
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parb_size = 1 << ((val & PCI_VC_CAP1_ARB_SIZE) >> 10);
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/* parb size (b) * number of phases / bits to byte / byte per dword */
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size = (parb_size * parb_phase) / 8 / 4;
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if (!size)
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return -EIO;
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/* update Port Arbitration Table */
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for (i = 0; i < size; i++)
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pci_write_config_dword(pcidev, pos + parb_offset + i * 4,
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parb_phase_value);
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/* set Load Port Arbitration Table bit to update the port arbitration */
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pci_read_config_dword(pcidev, pos + PCI_VC_RES_CTRL, &val);
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val |= PCI_VC_RES_CTRL_LOAD_TABLE;
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pci_write_config_dword(pcidev, pos + PCI_VC_RES_CTRL, val);
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/* poll Port Arbitration Status until H/W completes with the update */
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do {
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usleep_range(1000, 1005);
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pci_read_config_word(pcidev, pos + PCI_VC_RES_STATUS, &status);
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} while ((status & PCI_VC_RES_STATUS_TABLE) && --timeout);
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if (!timeout) {
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pr_err("port %s failed to load Port Arbitration Table\n",
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dev_name(&pcidev->dev));
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return -EIO;
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}
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/* update Port Arbitration Select field to select scheme */
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pci_read_config_dword(pcidev, pos + PCI_VC_RES_CTRL, &val);
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val &= ~PCI_VC_RES_CTRL_ARB_SELECT;
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val |= parb_select << 17;
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pci_write_config_dword(pcidev, pos + PCI_VC_RES_CTRL, val);
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return 0;
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}
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static int config_common_port_diode(struct device *dev, void *data)
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{
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struct pci_dev *pcidev = to_pci_dev(dev);
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int ret = 0;
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u32 addr, val;
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if (!pcidev) {
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pr_err("%s: port not found\n", __func__);
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return -ENODEV;
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}
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addr = 0x3c;
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ret = pci_read_config_dword(pcidev, addr, &val);
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if (ret) {
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pr_err("read fail: port %s read cfg addr:%x val:%x ret:%d\n",
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dev_name(&pcidev->dev), addr, val, ret);
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return ret;
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}
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val |= 1 << 17;
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ret = pci_write_config_dword(pcidev, addr, val);
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if (ret) {
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pr_err("write fail: port %s read cfg addr:%x val:%x ret:%d\n",
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dev_name(&pcidev->dev), addr, val, ret);
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return ret;
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}
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return 0;
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}
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static int config_upstream_port_diode(struct device *dev, void *data)
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{
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struct pci_dev *pcidev = to_pci_dev(dev);
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u32 addr, val;
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int ret;
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if (!pcidev) {
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pr_err("%s: port not found\n", __func__);
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return -ENODEV;
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}
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/* write cfg offset 74h.bit[7] = 1 */
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addr = 0x74;
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ret = pci_read_config_dword(pcidev, addr, &val);
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if (ret) {
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pr_err("read fail: port %s read cfg addr:%x val:%x ret:%d\n",
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dev_name(&pcidev->dev), addr, val, ret);
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return ret;
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}
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val |= 1 << 7;
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ret = pci_write_config_dword(pcidev, addr, val);
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if (ret) {
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pr_err("write fail: port %s write cfg addr:%x val:%x ret:%d\n",
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dev_name(&pcidev->dev), addr, val, ret);
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return ret;
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}
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ret = config_common_port_diode(dev, NULL);
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if (ret) {
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pr_err("%s: Applying common configuration failed\n", __func__);
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return ret;
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}
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/*
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* Update Port Arbitration table
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*
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* Port arbitation scheme: 3: WRR 128 Phase
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*
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* 4-bits per phase
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*
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* Every 8th phase will be for Port2 while the rest is for Port1
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* ex:
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* Phase[7]: Port2 Phase [6:0]: Port1
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* Phase[15]: Port2 Phase [14:8]: Port1
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* ...
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* Phase[127]: Port2 Phase [126:120]: Port1
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*/
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ret = config_port_arbitration(dev, 3, 0x21111111);
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if (ret) {
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pr_err("%s: Failed to setup Port Arbitration\n", __func__);
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return ret;
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}
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return 0;
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}
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static int config_downstream_port_1_diode(struct device *dev, void *data)
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{
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struct pci_dev *pcidev = to_pci_dev(dev);
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int ret;
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u32 addr, val;
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if (!pcidev) {
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pr_err("%s: port not found\n", __func__);
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return -ENODEV;
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}
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/* write cfg offset 6ch.bit[25] = 1 */
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addr = 0x6c;
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ret = pci_read_config_dword(pcidev, addr, &val);
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if (ret) {
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pr_err("read fail: port %s read cfg addr:%x val:%x ret:%d\n",
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dev_name(&pcidev->dev), addr, val, ret);
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return ret;
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}
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val |= 1 << 25;
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ret = pci_write_config_dword(pcidev, addr, val);
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if (ret) {
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pr_err("write fail: port %s write cfg addr:%x val:%x ret:%d\n",
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dev_name(&pcidev->dev), addr, val, ret);
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return ret;
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}
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/* write cfg offset 33ch.bit[2] = 1 */
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addr = 0x33c;
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ret = pci_read_config_dword(pcidev, addr, &val);
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if (ret) {
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pr_err("read fail: port %s read cfg addr:%x val:%x ret:%d\n",
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dev_name(&pcidev->dev), addr, val, ret);
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return ret;
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}
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val |= 1 << 2;
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ret = pci_write_config_dword(pcidev, addr, val);
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if (ret) {
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pr_err("write fail: port %s write cfg addr:%x val:%x ret:%d\n",
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dev_name(&pcidev->dev), addr, val, ret);
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return ret;
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}
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ret = config_common_port_diode(dev, NULL);
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if (ret) {
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pr_err("%s: Applying common configuration failed\n", __func__);
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return ret;
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}
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return 0;
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}
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struct pci_qcom_switch_errata errata[] = {
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[DIODE_ERRATA_0] = {config_upstream_port_diode},
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[DIODE_ERRATA_1] = {config_downstream_port_1_diode},
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[DIODE_ERRATA_2] = {config_common_port_diode},
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};
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static struct pci_device_id switch_qcom_pci_tbl[] = {
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{
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PCI_DEVICE(DIODE_VENDOR_ID, DIODE_DEVICE_ID),
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},
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{0},
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};
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MODULE_DEVICE_TABLE(pci, switch_qcom_pci_tbl);
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static int switch_qcom_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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int ret = 0, errata_num = 0;
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ret = of_property_read_u32((&pdev->dev)->of_node, "errata",
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&errata_num);
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if (ret) {
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pr_info("No erratas needed\n");
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return 0;
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}
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pr_info("Errata being requested: %d\n", errata_num);
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if (errata_num >= SWITCH_MAX) {
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pr_err("Invalid errata num:%d\n", errata_num);
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return -EINVAL;
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}
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ret = errata[errata_num].config_errata(&pdev->dev, NULL);
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if (ret) {
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pr_err("Error applying errata\n");
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return ret;
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}
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return 0;
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}
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static struct pci_driver switch_qcom_pci_driver = {
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.name = "pcie-qcom-switch",
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.id_table = switch_qcom_pci_tbl,
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.probe = switch_qcom_pci_probe,
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};
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static int __init switch_qcom_pci_init(void)
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{
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return pci_register_driver(&switch_qcom_pci_driver);
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}
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module_init(switch_qcom_pci_init);
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static void __exit switch_qcom_pci_exit(void)
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{
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return pci_unregister_driver(&switch_qcom_pci_driver);
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}
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module_exit(switch_qcom_pci_exit);
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