From e08df66270dc7bece1daeed30bd589b96015f08a Mon Sep 17 00:00:00 2001 From: Shefali Jain Date: Mon, 16 Apr 2018 14:06:57 +0530 Subject: [PATCH] clk: qcom: clk-debug: Add support for enable mask for debug clk The enable bit position could vary across targets. Add the en_mask where the enable bit position could be supplied for debug clock branch. Change-Id: I9e910f53e4a13f701a3a37b640c4f72da164f6af Signed-off-by: Shefali Jain --- drivers/clk/qcom/clk-debug.c | 12 ++++++++---- drivers/clk/qcom/clk-debug.h | 5 ++++- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/clk-debug.c b/drivers/clk/qcom/clk-debug.c index c67bb2bf2c69..2bcad2d0173a 100644 --- a/drivers/clk/qcom/clk-debug.c +++ b/drivers/clk/qcom/clk-debug.c @@ -200,17 +200,19 @@ static void enable_debug_clks(struct clk_debug_mux *meas, u8 index) { int dbg_cc = meas->parent[index].dbg_cc; + meas->en_mask = meas->en_mask ? meas->en_mask : CBCR_ENA; + if (dbg_cc != GCC) { /* Not all recursive muxes have a DEBUG clock. */ if (meas->parent[index].cbcr_offset != U32_MAX) regmap_update_bits(meas->regmap[dbg_cc], meas->parent[index].cbcr_offset, - CBCR_ENA, CBCR_ENA); + meas->en_mask, meas->en_mask); } /* Turn on the GCC_DEBUG_CBCR */ regmap_update_bits(meas->regmap[GCC], meas->cbcr_offset, - CBCR_ENA, CBCR_ENA); + meas->en_mask, meas->en_mask); } @@ -218,15 +220,17 @@ static void disable_debug_clks(struct clk_debug_mux *meas, u8 index) { int dbg_cc = meas->parent[index].dbg_cc; + meas->en_mask = meas->en_mask ? meas->en_mask : CBCR_ENA; + /* Turn off the GCC_DEBUG_CBCR */ regmap_update_bits(meas->regmap[GCC], meas->cbcr_offset, - CBCR_ENA, 0); + meas->en_mask, 0); if (dbg_cc != GCC) { if (meas->parent[index].cbcr_offset != U32_MAX) regmap_update_bits(meas->regmap[dbg_cc], meas->parent[index].cbcr_offset, - CBCR_ENA, 0); + meas->en_mask, 0); } } diff --git a/drivers/clk/qcom/clk-debug.h b/drivers/clk/qcom/clk-debug.h index eb40b32b66bf..6e23487751f3 100644 --- a/drivers/clk/qcom/clk-debug.h +++ b/drivers/clk/qcom/clk-debug.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2016, 2019, The Linux Foundation. All rights reserved. */ #ifndef __QCOM_CLK_DEBUG_H__ #define __QCOM_CLK_DEBUG_H__ @@ -88,6 +88,8 @@ struct clk_src { * @num_parents: number of parents * @regmap: regmaps of debug mux * @priv: private measure_clk_data to be used by debug mux + * @en_mask: indicates the enable bit mask at global clock + * controller debug mux. * @debug_offset: debug mux offset. * @post_div_offset: register with post-divider settings for the debug mux. * @cbcr_offset: branch register to turn on debug mux. @@ -106,6 +108,7 @@ struct clk_debug_mux { int num_parents; struct regmap **regmap; void *priv; + u32 en_mask; u32 debug_offset; u32 post_div_offset; u32 cbcr_offset;