A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-14 00:24:41 -04:00
Code Issues Projects Releases Packages Wiki Activity

staging: comedi: addi_apci_1564: use addi_tcw.h defines for timer

Browse source 
Use the generic TCW (timer/counter/watchdog) defines for the 12-bit timer.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2014-11-10 16:20:18 -07:00 • committed by Greg Kroah-Hartman
commit e23337dcbb
2 changed files with 20 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

24
drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c
View file

@ -28,14 +28,14 @@ static int apci1564_timer_insn_config(struct comedi_device *dev,
devpriv->tsk_current = current;
/* First Stop The Timer */
ctrl = inl(devpriv->timer + APCI1564_TIMER_CTRL_REG);
ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
ctrl &= 0xfffff9fe;
/* Stop The Timer */
outl(ctrl, devpriv->timer + APCI1564_TIMER_CTRL_REG);
outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
if (data[1] == 1) {
/* Enable timer int & disable all the other int sources */
outl(0x02, devpriv->timer + APCI1564_TIMER_CTRL_REG);
outl(0x02, devpriv->timer + ADDI_TCW_CTRL_REG);
outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
outl(0x0, dev->iobase + APCI1564_DO_IRQ_REG);
outl(0x0, dev->iobase + APCI1564_WDOG_IRQ_REG);
@ -49,20 +49,20 @@ static int apci1564_timer_insn_config(struct comedi_device *dev,
}
} else {
/* disable Timer interrupt */
outl(0x0, devpriv->timer + APCI1564_TIMER_CTRL_REG);
outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
}
/* Loading Timebase */
outl(data[2], devpriv->timer + APCI1564_TIMER_TIMEBASE_REG);
outl(data[2], devpriv->timer + ADDI_TCW_TIMEBASE_REG);
/* Loading the Reload value */
outl(data[3], devpriv->timer + APCI1564_TIMER_RELOAD_REG);
outl(data[3], devpriv->timer + ADDI_TCW_RELOAD_REG);
ctrl = inl(devpriv->timer + APCI1564_TIMER_CTRL_REG);
ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
ctrl &= 0xfff719e2;
ctrl |= (2 << 13) | 0x10;
/* mode 2 */
outl(ctrl, devpriv->timer + APCI1564_TIMER_CTRL_REG);
outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
return insn->n;
}
@ -75,7 +75,7 @@ static int apci1564_timer_insn_write(struct comedi_device *dev,
struct apci1564_private *devpriv = dev->private;
unsigned int ctrl;
ctrl = inl(devpriv->timer + APCI1564_TIMER_CTRL_REG);
ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
switch (data[1]) {
case 0: /* Stop The Timer */
ctrl &= 0xfffff9fe;
@ -85,7 +85,7 @@ static int apci1564_timer_insn_write(struct comedi_device *dev,
ctrl |= 0x1;
break;
}
outl(ctrl, devpriv->timer + APCI1564_TIMER_CTRL_REG);
outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
return insn->n;
}
@ -98,10 +98,10 @@ static int apci1564_timer_insn_read(struct comedi_device *dev,
struct apci1564_private *devpriv = dev->private;
/* Stores the status of the Timer */
data[0] = inl(devpriv->timer + APCI1564_TIMER_STATUS_REG) & 0x1;
data[0] = inl(devpriv->timer + ADDI_TCW_STATUS_REG) & 0x1;
/* Stores the Actual value of the Timer */
data[1] = inl(devpriv->timer + APCI1564_TIMER_REG);
data[1] = inl(devpriv->timer + ADDI_TCW_VAL_REG);
return insn->n;
}

23
drivers/staging/comedi/drivers/addi_apci_1564.c
View file

@ -28,6 +28,7 @@
#include "../comedidev.h"
#include "comedi_fc.h"
#include "addi_tcw.h"
#include "addi_watchdog.h"
/*
@ -94,18 +95,10 @@
#define APCI1564_WDOG_WARN_TIMEBASE_REG 0x40
/*
* devpriv->timer Register Map
* devpriv->timer Register Map (see addi_tcw.h for register/bit defines)
* PLD Revision 1.0 - PCI BAR 0 + 0x04
* PLD Revision 2.x - PCI BAR 0 + 0x48
*/
#define APCI1564_TIMER_REG 0x00
#define APCI1564_TIMER_RELOAD_REG 0x04
#define APCI1564_TIMER_TIMEBASE_REG 0x08
#define APCI1564_TIMER_CTRL_REG 0x0c
#define APCI1564_TIMER_STATUS_REG 0x10
#define APCI1564_TIMER_IRQ_REG 0x14
#define APCI1564_TIMER_WARN_TIMEVAL_REG 0x18 /* Rev 2.x only */
#define APCI1564_TIMER_WARN_TIMEBASE_REG 0x1c /* Rev 2.x only */
/*
* devpriv->counters Register Map
@ -150,8 +143,8 @@ static int apci1564_reset(struct comedi_device *dev)
addi_watchdog_reset(dev->iobase + APCI1564_WDOG_REG);
/* Reset the timer registers */
outl(0x0, devpriv->timer + APCI1564_TIMER_CTRL_REG);
outl(0x0, devpriv->timer + APCI1564_TIMER_RELOAD_REG);
outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
outl(0x0, devpriv->timer + ADDI_TCW_RELOAD_REG);
if (devpriv->counters) {
/* Reset the counter registers */
@ -187,17 +180,17 @@ static irqreturn_t apci1564_interrupt(int irq, void *d)
outl(status, dev->iobase + APCI1564_DI_IRQ_REG);
}
status = inl(devpriv->timer + APCI1564_TIMER_IRQ_REG);
status = inl(devpriv->timer + ADDI_TCW_IRQ_REG);
if (status & 0x01) {
/* Disable Timer Interrupt */
ctrl = inl(devpriv->timer + APCI1564_TIMER_CTRL_REG);
outl(0x0, devpriv->timer + APCI1564_TIMER_CTRL_REG);
ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
/* Send a signal to from kernel to user space */
send_sig(SIGIO, devpriv->tsk_current, 0);
/* Enable Timer Interrupt */
outl(ctrl, devpriv->timer + APCI1564_TIMER_CTRL_REG);
outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
}
if (devpriv->counters) {