mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 03:27:44 -04:00
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for 4.5 plus some 4.4 fixes.
The executive summary:
- ATH79 platform improvments, use DT bindings for the ATH79 USB PHY.
- Avoid useless rebuilds for zboot.
- jz4780: Add NEMC, BCH and NAND device tree nodes
- Initial support for the MicroChip's DT platform. As all the device
drivers are missing this is still of limited use.
- Some Loongson3 cleanups.
- The unavoidable whitespace polishing.
- Reduce clock skew when synchronizing the CPU cycle counters on CPU
startup.
- Add MIPS R6 fixes.
- Lots of cleanups across arch/mips as fallout from KVM.
- Lots of minor fixes and changes for IEEE 754-2008 support to the
FPU emulator / fp-assist software.
- Minor Ralink, BCM47xx and bcm963xx platform support improvments.
- Support SMP on BCM63168"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (84 commits)
MIPS: zboot: Add support for serial debug using the PROM
MIPS: zboot: Avoid useless rebuilds
MIPS: BMIPS: Enable ARCH_WANT_OPTIONAL_GPIOLIB
MIPS: bcm63xx: nvram: Remove unused bcm63xx_nvram_get_psi_size() function
MIPS: bcm963xx: Update bcm_tag field image_sequence
MIPS: bcm963xx: Move extended flash address to bcm_tag header file
MIPS: bcm963xx: Move Broadcom BCM963xx image tag data structure
MIPS: bcm63xx: nvram: Use nvram structure definition from header file
MIPS: bcm963xx: Add Broadcom BCM963xx board nvram data structure
MAINTAINERS: Add KVM for MIPS entry
MIPS: KVM: Add missing newline to kvm_err()
MIPS: Move KVM specific opcodes into asm/inst.h
MIPS: KVM: Use cacheops.h definitions
MIPS: Break down cacheops.h definitions
MIPS: Use EXCCODE_ constants with set_except_vector()
MIPS: Update trap codes
MIPS: Move Cause.ExcCode trap codes to mipsregs.h
MIPS: KVM: Make kvm_mips_{init,exit}() static
MIPS: KVM: Refactor added offsetof()s
MIPS: KVM: Convert EXPORT_SYMBOL to _GPL
...
This commit is contained in:
Linus Torvalds
commit
e2464688b5
130 changed files with 4923 additions and 676 deletions
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@ -130,6 +130,11 @@ config ORION_IRQCHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config PIC32_EVIC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config RENESAS_INTC_IRQPIN
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bool
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select IRQ_DOMAIN
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@ -58,3 +58,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
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obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
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obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
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obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
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obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
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324
drivers/irqchip/irq-pic32-evic.c
Normal file
324
drivers/irqchip/irq-pic32-evic.c
Normal file
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@ -0,0 +1,324 @@
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/*
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* Cristian Birsan <cristian.birsan@microchip.com>
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* Joshua Henderson <joshua.henderson@microchip.com>
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* Copyright (C) 2016 Microchip Technology Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irq.h>
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#include <asm/irq.h>
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#include <asm/traps.h>
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#include <asm/mach-pic32/pic32.h>
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#define REG_INTCON 0x0000
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#define REG_INTSTAT 0x0020
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#define REG_IFS_OFFSET 0x0040
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#define REG_IEC_OFFSET 0x00C0
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#define REG_IPC_OFFSET 0x0140
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#define REG_OFF_OFFSET 0x0540
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#define MAJPRI_MASK 0x07
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#define SUBPRI_MASK 0x03
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#define PRIORITY_MASK 0x1F
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#define PIC32_INT_PRI(pri, subpri) \
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((((pri) & MAJPRI_MASK) << 2) | ((subpri) & SUBPRI_MASK))
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struct evic_chip_data {
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u32 irq_types[NR_IRQS];
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u32 ext_irqs[8];
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};
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static struct irq_domain *evic_irq_domain;
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static void __iomem *evic_base;
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asmlinkage void __weak plat_irq_dispatch(void)
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{
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unsigned int irq, hwirq;
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hwirq = readl(evic_base + REG_INTSTAT) & 0xFF;
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irq = irq_linear_revmap(evic_irq_domain, hwirq);
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do_IRQ(irq);
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}
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static struct evic_chip_data *irqd_to_priv(struct irq_data *data)
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{
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return (struct evic_chip_data *)data->domain->host_data;
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}
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static int pic32_set_ext_polarity(int bit, u32 type)
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{
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/*
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* External interrupts can be either edge rising or edge falling,
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* but not both.
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*/
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON));
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break;
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case IRQ_TYPE_EDGE_FALLING:
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writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON));
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int pic32_set_type_edge(struct irq_data *data,
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unsigned int flow_type)
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{
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struct evic_chip_data *priv = irqd_to_priv(data);
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int ret;
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int i;
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if (!(flow_type & IRQ_TYPE_EDGE_BOTH))
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return -EBADR;
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/* set polarity for external interrupts only */
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for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
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if (priv->ext_irqs[i] == data->hwirq) {
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ret = pic32_set_ext_polarity(i + 1, flow_type);
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if (ret)
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return ret;
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}
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}
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irqd_set_trigger_type(data, flow_type);
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return IRQ_SET_MASK_OK;
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}
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static void pic32_bind_evic_interrupt(int irq, int set)
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{
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writel(set, evic_base + REG_OFF_OFFSET + irq * 4);
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}
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static void pic32_set_irq_priority(int irq, int priority)
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{
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u32 reg, shift;
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reg = irq / 4;
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shift = (irq % 4) * 8;
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writel(PRIORITY_MASK << shift,
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evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10));
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writel(priority << shift,
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evic_base + PIC32_SET(REG_IPC_OFFSET + reg * 0x10));
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}
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#define IRQ_REG_MASK(_hwirq, _reg, _mask) \
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do { \
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_reg = _hwirq / 32; \
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_mask = 1 << (_hwirq % 32); \
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} while (0)
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static int pic32_irq_domain_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct evic_chip_data *priv = d->host_data;
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struct irq_data *data;
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int ret;
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u32 iecclr, ifsclr;
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u32 reg, mask;
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ret = irq_map_generic_chip(d, virq, hw);
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if (ret)
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return ret;
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/*
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* Piggyback on xlate function to move to an alternate chip as necessary
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* at time of mapping instead of allowing the flow handler/chip to be
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* changed later. This requires all interrupts to be configured through
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* DT.
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*/
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if (priv->irq_types[hw] & IRQ_TYPE_SENSE_MASK) {
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data = irq_domain_get_irq_data(d, virq);
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irqd_set_trigger_type(data, priv->irq_types[hw]);
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irq_setup_alt_chip(data, priv->irq_types[hw]);
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}
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IRQ_REG_MASK(hw, reg, mask);
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iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10);
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ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10);
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/* mask and clear flag */
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writel(mask, evic_base + iecclr);
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writel(mask, evic_base + ifsclr);
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/* default priority is required */
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pic32_set_irq_priority(hw, PIC32_INT_PRI(2, 0));
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return ret;
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}
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int pic32_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_type)
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{
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struct evic_chip_data *priv = d->host_data;
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if (WARN_ON(intsize < 2))
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return -EINVAL;
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if (WARN_ON(intspec[0] >= NR_IRQS))
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return -EINVAL;
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*out_hwirq = intspec[0];
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*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
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priv->irq_types[intspec[0]] = intspec[1] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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static const struct irq_domain_ops pic32_irq_domain_ops = {
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.map = pic32_irq_domain_map,
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.xlate = pic32_irq_domain_xlate,
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};
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static void __init pic32_ext_irq_of_init(struct irq_domain *domain)
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{
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struct device_node *node = irq_domain_get_of_node(domain);
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struct evic_chip_data *priv = domain->host_data;
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struct property *prop;
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const __le32 *p;
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u32 hwirq;
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int i = 0;
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const char *pname = "microchip,external-irqs";
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of_property_for_each_u32(node, pname, prop, p, hwirq) {
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if (i >= ARRAY_SIZE(priv->ext_irqs)) {
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pr_warn("More than %d external irq, skip rest\n",
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ARRAY_SIZE(priv->ext_irqs));
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break;
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}
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priv->ext_irqs[i] = hwirq;
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i++;
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}
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}
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static int __init pic32_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_chip_generic *gc;
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struct evic_chip_data *priv;
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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int nchips, ret;
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int i;
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nchips = DIV_ROUND_UP(NR_IRQS, 32);
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evic_base = of_iomap(node, 0);
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if (!evic_base)
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return -ENOMEM;
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priv = kcalloc(nchips, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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ret = -ENOMEM;
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goto err_iounmap;
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}
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evic_irq_domain = irq_domain_add_linear(node, nchips * 32,
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&pic32_irq_domain_ops,
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priv);
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if (!evic_irq_domain) {
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ret = -ENOMEM;
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goto err_free_priv;
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}
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/*
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* The PIC32 EVIC has a linear list of irqs and the type of each
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* irq is determined by the hardware peripheral the EVIC is arbitrating.
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* These irq types are defined in the datasheet as "persistent" and
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* "non-persistent" which are mapped here to level and edge
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* respectively. To manage the different flow handler requirements of
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* each irq type, different chip_types are used.
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*/
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ret = irq_alloc_domain_generic_chips(evic_irq_domain, 32, 2,
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"evic-level", handle_level_irq,
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clr, 0, 0);
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if (ret)
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goto err_domain_remove;
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board_bind_eic_interrupt = &pic32_bind_evic_interrupt;
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for (i = 0; i < nchips; i++) {
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u32 ifsclr = PIC32_CLR(REG_IFS_OFFSET + (i * 0x10));
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u32 iec = REG_IEC_OFFSET + (i * 0x10);
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gc = irq_get_domain_generic_chip(evic_irq_domain, i * 32);
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gc->reg_base = evic_base;
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gc->unused = 0;
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/*
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* Level/persistent interrupts have a special requirement that
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* the condition generating the interrupt be cleared before the
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* interrupt flag (ifs) can be cleared. chip.irq_eoi is used to
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* complete the interrupt with an ack.
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*/
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gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
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gc->chip_types[0].handler = handle_fasteoi_irq;
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gc->chip_types[0].regs.ack = ifsclr;
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gc->chip_types[0].regs.mask = iec;
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gc->chip_types[0].chip.name = "evic-level";
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gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types[0].chip.flags = IRQCHIP_SKIP_SET_WAKE;
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/* Edge interrupts */
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gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
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gc->chip_types[1].handler = handle_edge_irq;
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gc->chip_types[1].regs.ack = ifsclr;
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gc->chip_types[1].regs.mask = iec;
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gc->chip_types[1].chip.name = "evic-edge";
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gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types[1].chip.irq_set_type = pic32_set_type_edge;
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gc->chip_types[1].chip.flags = IRQCHIP_SKIP_SET_WAKE;
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gc->private = &priv[i];
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}
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irq_set_default_host(evic_irq_domain);
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/*
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* External interrupts have software configurable edge polarity. These
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* interrupts are defined in DT allowing polarity to be configured only
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* for these interrupts when requested.
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*/
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pic32_ext_irq_of_init(evic_irq_domain);
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return 0;
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err_domain_remove:
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irq_domain_remove(evic_irq_domain);
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err_free_priv:
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kfree(priv);
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err_iounmap:
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iounmap(evic_base);
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return ret;
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}
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IRQCHIP_DECLARE(pic32_evic, "microchip,pic32mzda-evic", pic32_of_init);
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Loading…
Reference in a new issue