From 84a95d00e00bbbd42e8022377eb1c5739a31fa73 Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Fri, 7 May 2021 18:20:16 +0800 Subject: [PATCH] ARM: dts: msm: Fix compilation warnings for sa8155, sa8195 and sa6155 Fix compilation warnings for sa8155, sa8195 and sa6155. Change-Id: I6463b9106e2c40104720052b073455164e641df1 --- qcom/msm-arm-smmu-sdmshrike.dtsi | 56 ++++++++++++++++---------------- qcom/msm-arm-smmu-sm6150.dtsi | 20 ++++++------ qcom/msm-arm-smmu-sm8150-v2.dtsi | 28 ++++++++-------- qcom/msm-arm-smmu-sm8150.dtsi | 46 +++++++++++++------------- qcom/sa6155-adp-common.dtsi | 2 +- qcom/sa6155.dtsi | 2 +- qcom/sa6155p.dtsi | 4 +-- qcom/sa8155-adp-common.dtsi | 2 +- qcom/sa8155.dtsi | 10 +++--- qcom/sa8195-qupv3.dtsi | 18 +++++----- qcom/sa8195p-adp-common.dtsi | 4 +-- qcom/sa8195p.dtsi | 6 ++-- qcom/sdmshrike.dtsi | 32 +++++++++--------- qcom/sm6150-gpu.dtsi | 4 +-- qcom/sm6150-slpi-pinctrl.dtsi | 4 +-- qcom/sm6150.dtsi | 14 ++++---- qcom/sm8150-gpu.dtsi | 8 ++--- qcom/sm8150-pinctrl.dtsi | 2 +- qcom/sm8150-qupv3.dtsi | 16 ++++----- qcom/sm8150-slpi-pinctrl.dtsi | 4 +-- qcom/sm8150.dtsi | 10 +++--- 21 files changed, 146 insertions(+), 146 deletions(-) diff --git a/qcom/msm-arm-smmu-sdmshrike.dtsi b/qcom/msm-arm-smmu-sdmshrike.dtsi index 28a31ba15cd7..8788e684d9e6 100644 --- a/qcom/msm-arm-smmu-sdmshrike.dtsi +++ b/qcom/msm-arm-smmu-sdmshrike.dtsi @@ -1,9 +1,9 @@ #include &soc { - kgsl_smmu: kgsl-smmu@0x02CA0000 { + kgsl_smmu: kgsl-smmu@2ca0000 { compatible = "qcom,qsmmu-v500"; - reg = <0x02CA0000 0x10000>, + reg = <0x2ca0000 0x10000>, <0x2CC2000 0x20>; reg-names = "base", "tcu-base"; #iommu-cells = <2>; @@ -35,40 +35,40 @@ , ; - gfx_0_tbu: gfx_0_tbu@0x2CC5000 { + gfx_0_tbu: gfx_0_tbu@2cc5000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CC5000 0x1000>, - <0x2CC2200 0x8>; + reg = <0x2cc5000 0x1000>, + <0x2cc2200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; }; - gfx_1_tbu: gfx_1_tbu@0x2CC9000 { + gfx_1_tbu: gfx_1_tbu@2cc9000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CC9000 0x1000>, - <0x2CC2208 0x8>; + reg = <0x2cc9000 0x1000>, + <0x2cc2208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; }; - gfx_2_tbu: gfx_2_tbu@0x2CCD000 { + gfx_2_tbu: gfx_2_tbu@2ccd000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CCD000 0x1000>, - <0x2CC2210 0x8>; + reg = <0x2ccd000 0x1000>, + <0x2cc2210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; }; - gfx_3_tbu: gfx_3_tbu@0x2CD1000 { + gfx_3_tbu: gfx_3_tbu@2cd1000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CD1000 0x1000>, - <0x2CC2218 0x8>; + reg = <0x2cd1000 0x1000>, + <0x2cc2218 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0xC00 0x400>; }; }; - apps_smmu: apps-smmu@0x15000000 { + apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, <0x15182000 0x20>; @@ -213,7 +213,7 @@ interconnects = <&system_noc MASTER_GEM_NOC_SNOC &config_noc SLAVE_IMEM_CFG>; - anoc_1_tbu: anoc_1_tbu@0x15185000 { + anoc_1_tbu: anoc_1_tbu@15185000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15185000 0x1000>, <0x15182200 0x8>; @@ -226,7 +226,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_2_tbu: anoc_2_tbu@0x15189000 { + anoc_2_tbu: anoc_2_tbu@15189000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15189000 0x1000>, <0x15182208 0x8>; @@ -239,9 +239,9 @@ &config_noc SLAVE_IMEM_CFG>; }; - mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 { + mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x1518D000 0x1000>, + reg = <0x1518d000 0x1000>, <0x15182210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; @@ -252,7 +252,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15191000 0x1000>, <0x15182218 0x8>; @@ -265,7 +265,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - compute_dsp_1_tbu: compute_dsp_1_tbu@0x15195000 { + compute_dsp_1_tbu: compute_dsp_1_tbu@15195000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15195000 0x1000>, <0x15182220 0x8>; @@ -276,7 +276,7 @@ &compute_noc SLAVE_CDSP_MEM_NOC>; }; - compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15199000 0x1000>, <0x15182228 0x8>; @@ -287,9 +287,9 @@ &compute_noc SLAVE_CDSP_MEM_NOC>; }; - adsp_tbu: adsp_tbu@0x1519D000 { + adsp_tbu: adsp_tbu@1519d000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x1519D000 0x1000>, + reg = <0x1519d000 0x1000>, <0x15182230 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1800 0x400>; @@ -300,9 +300,9 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_pcie: anoc_pcie@151A1000 { + anoc_pcie: anoc_pcie@151a1000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x151A1000 0x1000>, + reg = <0x151a1000 0x1000>, <0x15182238 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1c00 0x400>; @@ -315,9 +315,9 @@ &config_noc SLAVE_IMEM_CFG>; }; - mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x151A5000 { + mnoc_sf_0_tbu: mnoc_sf_0_tbu@151a5000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x151A5000 0x1000>, + reg = <0x151a5000 0x1000>, <0x15182240 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x2000 0x400>; diff --git a/qcom/msm-arm-smmu-sm6150.dtsi b/qcom/msm-arm-smmu-sm6150.dtsi index ebf2aaeeaf3d..1fdde83c4c48 100644 --- a/qcom/msm-arm-smmu-sm6150.dtsi +++ b/qcom/msm-arm-smmu-sm6150.dtsi @@ -1,7 +1,7 @@ #include &soc { - kgsl_smmu: kgsl-smmu@0x50a0000 { + kgsl_smmu: kgsl-smmu@50a0000 { compatible = "qcom,qsmmu-v500"; reg = <0x50a0000 0x10000>, <0x50c2000 0x20>; @@ -35,7 +35,7 @@ , ; - gfx_0_tbu: gfx_0_tbu@0x50c5000 { + gfx_0_tbu: gfx_0_tbu@50c5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x50c5000 0x1000>, <0x50c2200 0x8>; @@ -43,7 +43,7 @@ qcom,stream-id-range = <0x0 0x400>; }; - gfx_1_tbu: gfx_1_tbu@0x50c9000 { + gfx_1_tbu: gfx_1_tbu@50c9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x50c9000 0x1000>, <0x50c2208 0x8>; @@ -52,7 +52,7 @@ }; }; - apps_smmu: apps-smmu@0x15000000 { + apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x80000>, <0x150c2000 0x20>; @@ -135,7 +135,7 @@ &config_noc SLAVE_IMEM_CFG>; qcom,active-only; - anoc_1_tbu: anoc_1_tbu@0x150c5000 { + anoc_1_tbu: anoc_1_tbu@150c5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150c5000 0x1000>, <0x150c2200 0x8>; @@ -148,7 +148,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_2_tbu: anoc_2_tbu@0x150c9000 { + anoc_2_tbu: anoc_2_tbu@150c9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150c9000 0x1000>, <0x150c2208 0x8>; @@ -161,7 +161,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 { + mnoc_hf_0_tbu: mnoc_hf_0_tbu@150cd000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150cd000 0x1000>, <0x150c2210 0x8>; @@ -174,7 +174,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d1000 { + mnoc_sf_0_tbu: mnoc_sf_0_tbu@150d1000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150d1000 0x1000>, <0x150c2218 0x8>; @@ -187,7 +187,7 @@ &mmss_noc SLAVE_MNOC_SF_MEM_NOC>; }; - compute_dsp_tbu: compute_dsp_tbu@0x150d5000 { + compute_dsp_tbu: compute_dsp_tbu@150d5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150d5000 0x1000>, <0x150c2220 0x8>; @@ -199,7 +199,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - adsp_tbu: adsp_tbu@0x150d9000 { + adsp_tbu: adsp_tbu@150d9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x150d9000 0x1000>, <0x150c2228 0x8>; diff --git a/qcom/msm-arm-smmu-sm8150-v2.dtsi b/qcom/msm-arm-smmu-sm8150-v2.dtsi index b694e0b014e8..9daee328b3f4 100644 --- a/qcom/msm-arm-smmu-sm8150-v2.dtsi +++ b/qcom/msm-arm-smmu-sm8150-v2.dtsi @@ -1,9 +1,9 @@ #include &soc { - kgsl_smmu: kgsl-smmu@0x02ca0000 { + kgsl_smmu: kgsl-smmu@2ca0000 { compatible = "qcom,qsmmu-v500"; - reg = <0x02ca0000 0x10000>, + reg = <0x2ca0000 0x10000>, <0x2cc2000 0x20>; reg-names = "base", "tcu-base"; #iommu-cells = <2>; @@ -34,7 +34,7 @@ , ; - gfx_0_tbu: gfx_0_tbu@0x2cc5000 { + gfx_0_tbu: gfx_0_tbu@2cc5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x2cc5000 0x1000>, <0x2cc2200 0x8>; @@ -42,7 +42,7 @@ qcom,stream-id-range = <0x0 0x400>; }; - gfx_1_tbu: gfx_1_tbu@0x2cc9000 { + gfx_1_tbu: gfx_1_tbu@2cc9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x2cc9000 0x1000>, <0x2cc2208 0x8>; @@ -51,7 +51,7 @@ }; }; - apps_smmu: apps-smmu@0x15000000 { + apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, <0x15182000 0x20>; @@ -150,7 +150,7 @@ &config_noc SLAVE_IMEM_CFG>; qcom,active-only; - anoc_1_tbu: anoc_1_tbu@0x15185000 { + anoc_1_tbu: anoc_1_tbu@15185000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15185000 0x1000>, <0x15182200 0x8>; @@ -163,7 +163,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_2_tbu: anoc_2_tbu@0x15189000 { + anoc_2_tbu: anoc_2_tbu@15189000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15189000 0x1000>, <0x15182208 0x8>; @@ -176,7 +176,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 { + mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x1518d000 0x1000>, <0x15182210 0x8>; @@ -189,7 +189,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15191000 0x1000>, <0x15182218 0x8>; @@ -202,7 +202,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - compute_dsp_1_tbu: compute_dsp_1_tbu@0x15195000 { + compute_dsp_1_tbu: compute_dsp_1_tbu@15195000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15195000 0x1000>, <0x15182220 0x8>; @@ -214,7 +214,7 @@ &compute_noc SLAVE_CDSP_MEM_NOC>; }; - compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15199000 0x1000>, <0x15182228 0x8>; @@ -226,7 +226,7 @@ &compute_noc SLAVE_CDSP_MEM_NOC>; }; - adsp_tbu: adsp_tbu@0x1519d000 { + adsp_tbu: adsp_tbu@1519d000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x1519d000 0x1000>, <0x15182230 0x8>; @@ -239,7 +239,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151a1000 { + anoc_1_pcie_tbu: anoc_1_pcie_tbu@151a1000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x151a1000 0x1000>, <0x15182238 0x8>; @@ -255,7 +255,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x151a5000 { + mnoc_sf_0_tbu: mnoc_sf_0_tbu@151a5000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x151a5000 0x1000>, <0x15182240 0x8>; diff --git a/qcom/msm-arm-smmu-sm8150.dtsi b/qcom/msm-arm-smmu-sm8150.dtsi index f279e5a55d46..71ae985d344c 100644 --- a/qcom/msm-arm-smmu-sm8150.dtsi +++ b/qcom/msm-arm-smmu-sm8150.dtsi @@ -1,10 +1,10 @@ #include &soc { - kgsl_smmu: kgsl-smmu@0x02CA0000 { + kgsl_smmu: kgsl-smmu@2ca0000 { compatible = "qcom,qsmmu-v500"; - reg = <0x02CA0000 0x10000>, - <0x2CC2000 0x20>; + reg = <0x2ca0000 0x10000>, + <0x2cc2000 0x20>; reg-names = "base", "tcu-base"; #iommu-cells = <2>; qcom,dynamic; @@ -35,24 +35,24 @@ , ; - gfx_0_tbu: gfx_0_tbu@0x2CC5000 { + gfx_0_tbu: gfx_0_tbu@2cc5000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CC5000 0x1000>, - <0x2CC2200 0x8>; + reg = <0x2cc5000 0x1000>, + <0x2cc2200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; }; - gfx_1_tbu: gfx_1_tbu@0x2CC9000 { + gfx_1_tbu: gfx_1_tbu@2cc9000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x2CC9000 0x1000>, - <0x2CC2208 0x8>; + reg = <0x2cc9000 0x1000>, + <0x2cc2208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; }; }; - apps_smmu: apps-smmu@0x15000000 { + apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, <0x15182000 0x20>; @@ -152,7 +152,7 @@ &config_noc SLAVE_IMEM_CFG>; qcom,active-only; - anoc_1_tbu: anoc_1_tbu@0x15185000 { + anoc_1_tbu: anoc_1_tbu@15185000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15185000 0x1000>, <0x15182200 0x8>; @@ -165,7 +165,7 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_2_tbu: anoc_2_tbu@0x15189000 { + anoc_2_tbu: anoc_2_tbu@15189000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15189000 0x1000>, <0x15182208 0x8>; @@ -179,9 +179,9 @@ }; - mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 { + mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518D000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x1518D000 0x1000>, + reg = <0x1518d000 0x1000>, <0x15182210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; @@ -192,7 +192,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15191000 0x1000>, <0x15182218 0x8>; @@ -205,7 +205,7 @@ &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; }; - mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15195000 { + mnoc_sf_0_tbu: mnoc_sf_0_tbu@15195000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15195000 0x1000>, <0x15182220 0x8>; @@ -218,7 +218,7 @@ &mmss_noc SLAVE_MNOC_SF_MEM_NOC>; }; - compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15199000 0x1000>, <0x15182228 0x8>; @@ -229,9 +229,9 @@ &compute_noc SLAVE_CDSP_MEM_NOC>; }; - adsp_tbu: adsp_tbu@0x1519D000 { + adsp_tbu: adsp_tbu@1519D000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x1519D000 0x1000>, + reg = <0x1519d000 0x1000>, <0x15182230 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1800 0x400>; @@ -242,9 +242,9 @@ &config_noc SLAVE_IMEM_CFG>; }; - anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151A1000 { + anoc_1_pcie_tbu: anoc_1_pcie_tbu@151A1000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x151A1000 0x1000>, + reg = <0x151a1000 0x1000>, <0x15182238 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1c00 0x400>; @@ -258,9 +258,9 @@ &config_noc SLAVE_IMEM_CFG>; }; - compute_dsp_1_tbu: compute_dsp_1_tbu@0x151A5000 { + compute_dsp_1_tbu: compute_dsp_1_tbu@151A5000 { compatible = "qcom,qsmmuv500-tbu"; - reg = <0x151A5000 0x1000>, + reg = <0x151a5000 0x1000>, <0x15182240 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x2000 0x400>; diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index ff23e07f3486..5a65e70dae2b 100644 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -92,7 +92,7 @@ }; }; - ethqos_hw: qcom,ethernet@00020000 { + ethqos_hw: qcom,ethernet@20000 { compatible = "qcom,stmmac-ethqos"; qcom,arm-smmu; emac-core-version = <0x20030001>; diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index d3b627917396..018ff859c0ef 100644 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -203,7 +203,7 @@ }; &reserved_memory { - uefi_log: uefi_log@0x9241C000 { + uefi_log: uefi_log@9241C000 { reg = <0x0 0x9241C000 0x0 0x10000>; label = "uefi_log"; }; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index cdb73870c1fc..ec2fa6bae6dd 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -41,10 +41,10 @@ ranges; }; - hsi2s: qcom,hsi2s { + hsi2s: qcom,hsi2s@1b40000 { compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; number-of-interfaces = <2>; - reg = <0x1B40000 0x28000>; + reg = <0x1b40000 0x28000>; reg-names = "lpa_if"; interrupts = ; clocks = <&gcc GCC_SDR_CORE_CLK>, diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index f9d32f4980b8..5161e34ca504 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -106,7 +106,7 @@ status = "ok"; }; - qcom,spss@1880000 { + qcom,spss@188101c { status = "ok"; }; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 78933e085cd0..f47e907fc63e 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -120,7 +120,7 @@ }; }; - ethqos_hw: qcom,ethernet@00020000 { + ethqos_hw: qcom,ethernet@20000 { compatible = "qcom,stmmac-ethqos"; qcom,arm-smmu; reg = <0x20000 0x10000>, @@ -204,11 +204,11 @@ mbox-names = "aop"; }; - hsi2s: qcom,hsi2s { + hsi2s: qcom,hsi2s@172c0000 { compatible = "qcom,sa8155-hsi2s", "qcom,hsi2s"; number-of-interfaces = <3>; - reg = <0x172C0000 0x28000>, - <0x17080000 0xE000>; + reg = <0x172c0000 0x28000>, + <0x17080000 0xe000>; reg-names = "lpa_if", "lpass_tcsr"; interrupts = ; number-of-rate-detectors = <2>; @@ -377,7 +377,7 @@ */ /delete-node/ pil_wlan_fw_mem; - uefi_log: uefi_log@0x9241C000 { + uefi_log: uefi_log@9241C000 { reg = <0x0 0x9241C000 0x0 0x10000>; label = "uefi_log"; }; diff --git a/qcom/sa8195-qupv3.dtsi b/qcom/sa8195-qupv3.dtsi index ce4ce38db758..02672c886918 100644 --- a/qcom/sa8195-qupv3.dtsi +++ b/qcom/sa8195-qupv3.dtsi @@ -378,7 +378,7 @@ }; /* Debug UART Instance for CDP/MTP platform */ - qupv3_se12_2uart: qcom,qup_uart@0xa90000 { + qupv3_se12_2uart: qcom,qup_uart@a90000 { compatible = "qcom,msm-geni-console"; reg = <0xa90000 0x4000>; reg-names = "se_phys"; @@ -395,7 +395,7 @@ }; /* 4-wire UART */ - qupv3_se13_4uart: qcom,qup_uart@0xc8c000 { + qupv3_se13_4uart: qcom,qup_uart@c8c000 { compatible = "qcom,msm-geni-serial-hs"; reg = <0xc8c000 0x4000>; reg-names = "se_phys"; @@ -417,7 +417,7 @@ status = "disabled"; }; - qupv3_se16_2uart: qcom,qup_uart@0xa94000 { + qupv3_se16_2uart: qcom,qup_uart@a94000 { compatible = "qcom,msm-geni-serial-hs"; reg = <0xa94000 0x4000>; reg-names = "se_phys"; @@ -646,7 +646,7 @@ status = "disabled"; }; - qupv3_se14_i2c: i2c@0xc90000 { + qupv3_se14_i2c: i2c@c90000 { compatible = "qcom,i2c-geni"; reg = <0xc90000 0x4000>; interrupts = ; @@ -663,7 +663,7 @@ status = "disabled"; }; - qupv3_se15_i2c: i2c@0xc94000 { + qupv3_se15_i2c: i2c@c94000 { compatible = "qcom,i2c-geni"; reg = <0xc94000 0x4000>; interrupts = ; @@ -680,7 +680,7 @@ status = "disabled"; }; - qupv3_se16_i2c: i2c@0xa94000 { + qupv3_se16_i2c: i2c@a94000 { compatible = "qcom,i2c-geni"; reg = <0xa94000 0x4000>; interrupts = ; @@ -697,7 +697,7 @@ status = "disabled"; }; - qupv3_se17_i2c: i2c@0xc80000 { + qupv3_se17_i2c: i2c@c80000 { compatible = "qcom,i2c-geni"; reg = <0xc80000 0x4000>; interrupts = ; @@ -714,7 +714,7 @@ status = "disabled"; }; - qupv3_se18_i2c: i2c@0xc84000 { + qupv3_se18_i2c: i2c@c84000 { compatible = "qcom,i2c-geni"; reg = <0xc84000 0x4000>; interrupts = ; @@ -731,7 +731,7 @@ status = "disabled"; }; - qupv3_se19_i2c: i2c@0xc88000 { + qupv3_se19_i2c: i2c@c88000 { compatible = "qcom,i2c-geni"; reg = <0xc88000 0x4000>; interrupts = ; diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index 2812da0bfcb4..1dab6e7db843 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -62,7 +62,7 @@ status = "ok"; status = "ok"; }; - qcom,spss@1880000 { + qcom,spss@188101c { status = "ok"; }; @@ -128,7 +128,7 @@ status = "ok"; }; }; - ethqos_hw: qcom,ethernet@00020000 { + ethqos_hw: qcom,ethernet@20000 { compatible = "qcom,stmmac-ethqos"; qcom,arm-smmu; emac-core-version = <0x20010001>; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index f948d707cf54..af53e61269e0 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -30,11 +30,11 @@ ranges; }; - hsi2s: qcom,hsi2s { + hsi2s: qcom,hsi2s@172c0000 { compatible = "qcom,sa8195-hsi2s", "qcom,hsi2s"; number-of-interfaces = <3>; - reg = <0x172C0000 0x28000>, - <0x17080000 0xE000>; + reg = <0x172c0000 0x28000>, + <0x17080000 0xe000>; reg-names = "lpa_if", "lpass_tcsr"; interrupts = ; number-of-rate-detectors = <2>; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index f9963d44fc0b..39abaf3c7b80 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -321,52 +321,52 @@ reg = <0x0 0x8bc00000 0x0 0x180000>; }; - pil_npu_mem: pil_npu_region@0x8bd80000 { + pil_npu_mem: pil_npu_region@8bd80000 { no-map; reg = <0x0 0x8bd80000 0x0 0x80000>; }; - pil_adsp_mem: pil_adsp_region@0x8be00000 { + pil_adsp_mem: pil_adsp_region@8be00000 { no-map; reg = <0x0 0x8be00000 0x0 0x1a00000>; }; - pil_modem_mem: modem_region@0x8d800000 { + pil_modem_mem: modem_region@8d800000 { no-map; reg = <0x0 0x8d800000 0x0 0x9600000>; }; - pil_video_mem: pil_video_region@0x96e00000 { + pil_video_mem: pil_video_region@96e00000 { no-map; reg = <0x0 0x96e00000 0x0 0x500000>; }; - pil_slpi_mem: pil_slpi_region@0x97300000 { + pil_slpi_mem: pil_slpi_region@97300000 { no-map; reg = <0x0 0x97300000 0x0 0x1400000>; }; - pil_ipa_fw_mem: pil_ipa_fw_region@0x98700000 { + pil_ipa_fw_mem: pil_ipa_fw_region@98700000 { no-map; reg = <0x0 0x98700000 0x0 0x10000>; }; - pil_ipa_gsi_mem: pil_ipa_gsi_region@0x98710000 { + pil_ipa_gsi_mem: pil_ipa_gsi_region@98710000 { no-map; reg = <0x0 0x98710000 0x0 0x5000>; }; - pil_gpu_mem: pil_gpu_region@0x98715000 { + pil_gpu_mem: pil_gpu_region@98715000 { no-map; reg = <0x0 0x98715000 0x0 0x2000>; }; - pil_spss_mem: pil_spss_region@0x98800000 { + pil_spss_mem: pil_spss_region@98800000 { no-map; reg = <0x0 0x98800000 0x0 0x100000>; }; - pil_cdsp_mem: cdsp_regions@0x98900000 { + pil_cdsp_mem: cdsp_regions@98900000 { no-map; reg = <0x0 0x98900000 0x0 0x1400000>; }; @@ -380,12 +380,12 @@ }; - cont_splash_memory: cont_splash_region@0x9c000000 { + cont_splash_memory: cont_splash_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x02400000>; label = "cont_splash_region"; }; - disp_rdump_memory: disp_rdump_region@0x9c000000 { + disp_rdump_memory: disp_rdump_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x02400000>; label = "disp_rdump_region"; }; @@ -445,7 +445,7 @@ size = <0 0x2400000>; }; - uefi_log: uefi_log@0x8bc00000 { + uefi_log: uefi_log@8bc00000 { reg = <0x0 0x8bc00000 0x0 0x10000>; label = "uefi_log"; }; @@ -543,7 +543,7 @@ clock-frequency = <19200000>; }; - timer@0x17c20000 { + timer@17c20000 { #address-cells = <1>; #size-cells = <1>; ranges; @@ -551,7 +551,7 @@ reg = <0x17c20000 0x1000>; clock-frequency = <19200000>; - frame@0x17c21000 { + frame@17c21000 { frame-number = <0>; interrupts = <0 7 0x4>, <0 6 0x4>; @@ -2334,7 +2334,7 @@ memory-region = <&pil_npu_mem>; }; - qcom,spss@1880000 { + qcom,spss@188101c { compatible = "qcom,pil-tz-generic"; reg = <0x188101c 0x4>, <0x1881024 0x4>, diff --git a/qcom/sm6150-gpu.dtsi b/qcom/sm6150-gpu.dtsi index b878a008e0d8..f888e6fa49e1 100644 --- a/qcom/sm6150-gpu.dtsi +++ b/qcom/sm6150-gpu.dtsi @@ -604,10 +604,10 @@ }; }; - kgsl_msm_iommu: qcom,kgsl-iommu@0x050a0000 { + kgsl_msm_iommu: qcom,kgsl-iommu@50a0000 { compatible = "qcom,kgsl-smmu-v2"; - reg = <0x050a0000 0x10000>; + reg = <0x50a0000 0x10000>; gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; diff --git a/qcom/sm6150-slpi-pinctrl.dtsi b/qcom/sm6150-slpi-pinctrl.dtsi index 32d250433a47..45b9d0510149 100644 --- a/qcom/sm6150-slpi-pinctrl.dtsi +++ b/qcom/sm6150-slpi-pinctrl.dtsi @@ -1,8 +1,8 @@ &soc { - slpi_tlmm: slpi_pinctrl@62B40000 { + slpi_tlmm: slpi_pinctrl@62b40000 { compatible = "qcom,slpi-pinctrl"; - reg = <0x62B40000 0x20000>; + reg = <0x62b40000 0x20000>; qcom,num-pins = <32>; clock-names = "ssc-clk"; clocks = <&scc SCC_QUPV3_S_HCLK_CLK>; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 9691fa618cc1..c51c34a39596 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -352,17 +352,17 @@ reg = <0x0 0x95900000 0x0 0x1e00000>; }; - pil_ipa_fw_mem: ips_fw_region@0x97700000 { + pil_ipa_fw_mem: ips_fw_region@97700000 { no-map; reg = <0x0 0x97700000 0x0 0x10000>; }; - pil_ipa_gsi_mem: ipa_gsi_region@0x97710000 { + pil_ipa_gsi_mem: ipa_gsi_region@97710000 { no-map; reg = <0x0 0x97710000 0x0 0x5000>; }; - pil_gpu_mem: gpu_region@0x97715000 { + pil_gpu_mem: gpu_region@97715000 { no-map; reg = <0x0 0x97715000 0x0 0x2000>; }; @@ -375,7 +375,7 @@ size = <0x0 0x1400000>; }; - cdsp_sec_mem: cdsp_sec_regions@0x9f800000 { + cdsp_sec_mem: cdsp_sec_regions@9f800000 { no-map; reg = <0x0 0x9f800000 0x0 0x1e00000>; }; @@ -497,7 +497,7 @@ clock-frequency = <19200000>; }; - timer@0x17c20000 { + timer@17c20000 { #address-cells = <1>; #size-cells = <1>; ranges; @@ -505,7 +505,7 @@ reg = <0x17c20000 0x1000>; clock-frequency = <19200000>; - frame@0x17c21000 { + frame@17c21000 { frame-number = <0>; interrupts = <0 8 0x4>, <0 6 0x4>; @@ -932,7 +932,7 @@ &mc_virt SLAVE_EBI1>; }; - qcom,mpm2-sleep-counter@0xc221000 { + qcom,mpm2-sleep-counter@c221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; clock-frequency = <32768>; diff --git a/qcom/sm8150-gpu.dtsi b/qcom/sm8150-gpu.dtsi index 6538058362f5..f8523ca53eb9 100644 --- a/qcom/sm8150-gpu.dtsi +++ b/qcom/sm8150-gpu.dtsi @@ -9,7 +9,7 @@ memory-region = <&pil_gpu_mem>; }; - msm_gpu: qcom,kgsl-3d0@2C00000 { + msm_gpu: qcom,kgsl-3d0@2c00000 { label = "kgsl-3d0"; compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; status = "ok"; @@ -219,10 +219,10 @@ }; - kgsl_msm_iommu: qcom,kgsl-iommu@0x02CA0000 { + kgsl_msm_iommu: qcom,kgsl-iommu@2ca0000 { compatible = "qcom,kgsl-smmu-v2"; - reg = <0x02CA0000 0x10000>; + reg = <0x2ca0000 0x10000>; gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; @@ -239,7 +239,7 @@ }; }; - gmu: qcom,gmu@0x2C6A000 { + gmu: qcom,gmu@2c6a000 { compatible = "qcom,gpu-gmu"; reg = <0x2c6a000 0x30000>, diff --git a/qcom/sm8150-pinctrl.dtsi b/qcom/sm8150-pinctrl.dtsi index ed449a36f0dd..c8eea6ee4ca2 100644 --- a/qcom/sm8150-pinctrl.dtsi +++ b/qcom/sm8150-pinctrl.dtsi @@ -1,5 +1,5 @@ &soc { - tlmm: pinctrl@03000000 { + tlmm: pinctrl@3100000 { compatible = "qcom,sm8150-pinctrl"; reg = <0x03100000 0x300000>, <0x03500000 0x300000>, diff --git a/qcom/sm8150-qupv3.dtsi b/qcom/sm8150-qupv3.dtsi index 74b51b054ad7..c902b9b75aec 100644 --- a/qcom/sm8150-qupv3.dtsi +++ b/qcom/sm8150-qupv3.dtsi @@ -359,7 +359,7 @@ }; /* Debug UART Instance for CDP/MTP platform */ - qupv3_se12_2uart: qcom,qup_uart@0xa90000 { + qupv3_se12_2uart: qcom,qup_uart@a90000 { compatible = "qcom,msm-geni-console"; reg = <0xa90000 0x4000>; reg-names = "se_phys"; @@ -376,7 +376,7 @@ }; /* 4-wire UART */ - qupv3_se13_4uart: qcom,qup_uart@0xc8c000 { + qupv3_se13_4uart: qcom,qup_uart@c8c000 { compatible = "qcom,msm-geni-serial-hs"; reg = <0xc8c000 0x4000>; reg-names = "se_phys"; @@ -611,7 +611,7 @@ status = "disabled"; }; - qupv3_se14_i2c: i2c@0xc90000 { + qupv3_se14_i2c: i2c@c90000 { compatible = "qcom,i2c-geni"; reg = <0xc90000 0x4000>; interrupts = ; @@ -628,7 +628,7 @@ status = "disabled"; }; - qupv3_se15_i2c: i2c@0xc94000 { + qupv3_se15_i2c: i2c@c94000 { compatible = "qcom,i2c-geni"; reg = <0xc94000 0x4000>; interrupts = ; @@ -645,7 +645,7 @@ status = "disabled"; }; - qupv3_se16_i2c: i2c@0xa94000 { + qupv3_se16_i2c: i2c@a94000 { compatible = "qcom,i2c-geni"; reg = <0xa94000 0x4000>; interrupts = ; @@ -662,7 +662,7 @@ status = "disabled"; }; - qupv3_se17_i2c: i2c@0xc80000 { + qupv3_se17_i2c: i2c@c80000 { compatible = "qcom,i2c-geni"; reg = <0xc80000 0x4000>; interrupts = ; @@ -679,7 +679,7 @@ status = "disabled"; }; - qupv3_se18_i2c: i2c@0xc84000 { + qupv3_se18_i2c: i2c@c84000 { compatible = "qcom,i2c-geni"; reg = <0xc84000 0x4000>; interrupts = ; @@ -696,7 +696,7 @@ status = "disabled"; }; - qupv3_se19_i2c: i2c@0xc88000 { + qupv3_se19_i2c: i2c@c88000 { compatible = "qcom,i2c-geni"; reg = <0xc88000 0x4000>; interrupts = ; diff --git a/qcom/sm8150-slpi-pinctrl.dtsi b/qcom/sm8150-slpi-pinctrl.dtsi index 2dfaa98271d3..6ddc10b4dc0c 100644 --- a/qcom/sm8150-slpi-pinctrl.dtsi +++ b/qcom/sm8150-slpi-pinctrl.dtsi @@ -1,7 +1,7 @@ &soc { - slpi_tlmm: slpi_pinctrl@02B40000 { + slpi_tlmm: slpi_pinctrl@2b40000 { compatible = "qcom,slpi-pinctrl"; - reg = <0x2B40000 0x20000>; + reg = <0x2b40000 0x20000>; clock-names = "ssc-clk"; clocks = <&scc SCC_QUPV3_S_HCLK_CLK>; qcom,num-pins = <14>; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 719f983fc39f..10fb995559ec 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -525,7 +525,7 @@ clock-frequency = <19200000>; }; - timer@0x17c20000 { + timer@17c20000 { #address-cells = <1>; #size-cells = <1>; ranges; @@ -533,7 +533,7 @@ reg = <0x17c20000 0x1000>; clock-frequency = <19200000>; - frame@0x17c21000 { + frame@17c21000 { frame-number = <0>; interrupts = <0 8 0x4>, <0 6 0x4>; @@ -1105,7 +1105,7 @@ status = "disabled"; }; - cpucc: syscon@182a0018 { + cpucc: syscon@182a0000 { compatible = "syscon"; reg = <0x182a0000 0x4>; }; @@ -1240,7 +1240,7 @@ thermal_zones: thermal-zones { }; - osm_l3: interconnect@0x18321000 { + osm_l3: interconnect@18321000 { reg = <0x18321000 0x1400>; compatible = "qcom,sm8150-osm-l3"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; @@ -2228,7 +2228,7 @@ mbox-names = "slpi-pil"; }; - qcom,spss@1880000 { + qcom,spss@188101c { compatible = "qcom,pil-tz-generic"; reg = <0x188101c 0x4>, <0x1881024 0x4>,