mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 00:24:41 -04:00
Merge "ARM: dts: msm: Add pinctrl node for TLMM on Shima SoC"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
e43fb77888
9 changed files with 557 additions and 0 deletions
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@ -50,6 +50,9 @@ SoCs:
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- LAHAINA
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compatible = "qcom,lahaina"
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- SHIMA
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compatible = "qcom,shima"
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- LITO
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compatible = "qcom,lito"
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@ -173,6 +176,7 @@ compatible = "qcom,lahaina-mtp"
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compatible = "qcom,lahaina-cdp"
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compatible = "qcom,lahaina-qrd"
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compatible = "qcom,lahaina-qrd-module"
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compatible = "qcom,shima-rumi"
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compatible = "qcom,lito-rumi"
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compatible = "qcom,lito-mtp"
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compatible = "qcom,lito-cdp"
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191
bindings/pinctrl/qcom,shima-pinctrl.txt
Normal file
191
bindings/pinctrl/qcom,shima-pinctrl.txt
Normal file
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@ -0,0 +1,191 @@
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Qualcomm Technologies, Inc. SHIMA TLMM block
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This binding describes the Top Level Mode Multiplexer block found in the
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SHIMA platform.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,shima-pinctrl"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: the base address and size of the TLMM register space.
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the TLMM summary IRQ.
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- interrupt-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as an interrupt controller
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- #interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/interrupt-controller/irq.h>
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- gpio-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as a gpio controller
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- #gpio-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/gpio/gpio.h>
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- wakeup-parent:
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Usage: optional
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Value type: <phandle>
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Definition: A phandle to the wakeup interrupt controller for the SoC.
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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- pins:
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Usage: required
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Value type: <string-array>
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Definition: List of gpio pins affected by the properties specified in
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this subnode.
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Valid pins are:
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gpio0-gpio203
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Supports mux, bias and drive-strength
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sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
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sdc2_data sdc1_rclk
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Supports bias and drive-strength
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- function:
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Usage: required
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Value type: <string>
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Definition: Specify the alternative function to be configured for the
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specified pins. Functions are only valid for gpio pins.
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Valid values are:
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blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
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bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
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qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
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dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
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blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
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mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
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atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
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cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
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pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
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qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
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qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
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atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
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atest_usb20, atest_char0, dac_calib10, qdss_stm10,
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qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
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blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
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qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
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qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
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dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
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qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
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dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
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dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
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dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
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dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
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sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
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qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
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uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
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blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
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qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
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blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
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cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
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blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
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qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
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isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
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qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
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sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
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gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
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qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
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tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
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qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
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sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
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sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
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ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
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blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
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pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
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qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
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qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
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gpio
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- bias-disable:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as no pull.
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- bias-pull-down:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull down.
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- bias-pull-up:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull up.
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- output-high:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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high.
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Not valid for sdc pins.
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- output-low:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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low.
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Not valid for sdc pins.
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- drive-strength:
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Usage: optional
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Value type: <u32>
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Definition: Selects the drive strength for the specified pins, in mA.
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Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
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Example:
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tlmm: pinctrl@0f000000 {
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compatible = "qcom,shima-pinctrl";
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reg = <0x0f000000 0x1000000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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@ -26,6 +26,15 @@ endif
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dtb-$(CONFIG_ARCH_QTI_VM) += trustedvm.dtb
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ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
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dtbo-$(CONFIG_ARCH_SHIMA) += \
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shima-rumi-overlay.dtbo
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shima-rumi-overlay.dtbo-base := shima.dtb
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else
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dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb
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endif
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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12
qcom/shima-pinctrl.dtsi
Normal file
12
qcom/shima-pinctrl.dtsi
Normal file
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@ -0,0 +1,12 @@
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&soc {
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tlmm: pinctrl@f000000 {
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compatible = "qcom,shima-pinctrl";
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reg = <0x0f000000 0x1000000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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10
qcom/shima-rumi-overlay.dts
Normal file
10
qcom/shima-rumi-overlay.dts
Normal file
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@ -0,0 +1,10 @@
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/dts-v1/;
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/plugin/;
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#include "shima-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Shima RUMI";
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compatible = "qcom,shima-rumi", "qcom,shima", "qcom,rumi";
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qcom,board-id = <0x1000F 0>;
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};
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11
qcom/shima-rumi.dts
Normal file
11
qcom/shima-rumi.dts
Normal file
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@ -0,0 +1,11 @@
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/dts-v1/;
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/memreserve/ 0x90000000 0x00000100;
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#include "shima.dtsi"
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#include "shima-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Shima RUMI";
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compatible = "qcom,shima-rumi", "qcom,shima", "qcom,rumi";
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qcom,board-id = <0x1000F 0>;
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};
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13
qcom/shima-rumi.dtsi
Normal file
13
qcom/shima-rumi.dtsi
Normal file
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@ -0,0 +1,13 @@
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&soc {
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timer {
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clock-frequency = <5000000>;
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};
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timer@17c20000 {
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clock-frequency = <5000000>;
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};
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wdog: qcom,wdt@17c10000 {
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status = "disabled";
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};
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};
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9
qcom/shima.dts
Normal file
9
qcom/shima.dts
Normal file
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@ -0,0 +1,9 @@
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/dts-v1/;
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#include "shima.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Shima SoC";
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compatible = "qcom,shima";
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qcom,board-id = <0 0>;
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};
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298
qcom/shima.dtsi
Normal file
298
qcom/shima.dtsi
Normal file
|
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@ -0,0 +1,298 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm Technologies, Inc. Shima";
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compatible = "qcom,shima";
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qcom,msm-id = <450 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x200000>;
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
|
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
|
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
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};
|
||||
};
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CPU2: cpu@200 {
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device_type = "cpu";
|
||||
compatible = "qcom,kryo";
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reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
d-cache-size = <0x8000>;
|
||||
i-cache-size = <0x8000>;
|
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next-level-cache = <&L2_2>;
|
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L2_2: l2-cache {
|
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compatible = "arm,arch-cache";
|
||||
cache-size = <0x20000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
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device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
d-cache-size = <0x8000>;
|
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i-cache-size = <0x8000>;
|
||||
next-level-cache = <&L2_3>;
|
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L2_3: l2-cache {
|
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compatible = "arm,arch-cache";
|
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cache-size = <0x20000>;
|
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cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
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||||
|
||||
CPU4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x400>;
|
||||
enable-method = "psci";
|
||||
d-cache-size = <0x8000>;
|
||||
i-cache-size = <0x8000>;
|
||||
next-level-cache = <&L2_4>;
|
||||
L2_4: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x40000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x500>;
|
||||
enable-method = "psci";
|
||||
d-cache-size = <0x8000>;
|
||||
i-cache-size = <0x8000>;
|
||||
next-level-cache = <&L2_5>;
|
||||
L2_5: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x40000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x600>;
|
||||
enable-method = "psci";
|
||||
d-cache-size = <0x8000>;
|
||||
i-cache-size = <0x8000>;
|
||||
next-level-cache = <&L2_6>;
|
||||
L2_6: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x40000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x700>;
|
||||
enable-method = "psci";
|
||||
d-cache-size = <0x8000>;
|
||||
i-cache-size = <0x8000>;
|
||||
next-level-cache = <&L2_7>;
|
||||
L2_7: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x80000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU4>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU5>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU6>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster2 {
|
||||
|
||||
core0 {
|
||||
cpu = <&CPU7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
|
||||
chosen { };
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
intc: interrupt-controller@17a00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x20000>;
|
||||
reg = <0x17a00000 0x10000>, /* GICD */
|
||||
<0x17a60000 0x100000>; /* GICR * 8 */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
wdog: qcom,wdt@17c10000 {
|
||||
compatible = "qcom,msm-watchdog";
|
||||
reg = <0x17c10000 0x1000>;
|
||||
reg-names = "wdt-base";
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,bark-time = <11000>;
|
||||
qcom,pet-time = <9360>;
|
||||
qcom,ipi-ping;
|
||||
qcom,wakeup-enable;
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
memtimer: timer@17c20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x17c20000 0x1000>;
|
||||
clock-frequency = <19200000>;
|
||||
|
||||
frame@17c21000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17c21000 0x1000>,
|
||||
<0x17c22000 0x1000>;
|
||||
};
|
||||
|
||||
frame@17c23000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17c23000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c25000 {
|
||||
frame-number = <2>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17c25000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c27000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17c27000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c29000 {
|
||||
frame-number = <4>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17c29000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c2b000 {
|
||||
frame-number = <5>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17c2b000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c2d000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17c2d000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "shima-pinctrl.dtsi"
|
||||
Loading…
Reference in a new issue