diff --git a/bengal-camera-sensor-idp.dtsi b/bengal-camera-sensor-idp.dtsi index 48f40a98c4a5..b52eee3e7d84 100644 --- a/bengal-camera-sensor-idp.dtsi +++ b/bengal-camera-sensor-idp.dtsi @@ -1,88 +1,162 @@ #include &soc { - led_flash_rear: qcom,camera-flash@0 { - cell-index = <0>; - compatible = "qcom,camera-flash"; - flash-source = <&pmi632_flash0 &pmi632_flash1>; - torch-source = <&pmi632_torch0 &pmi632_torch1>; - switch-source = <&pmi632_switch0 &pmi632_switch0>; - status = "ok"; - }; - - led_flash_rear_aux: qcom,camera-flash@1 { - cell-index = <1>; - compatible = "qcom,camera-flash"; - flash-source = <&pmi632_flash0 &pmi632_flash1>; - torch-source = <&pmi632_torch0 &pmi632_torch1>; - switch-source = <&pmi632_switch0 &pmi632_switch0>; - status = "ok"; - }; - - led_flash_rear_aux2: qcom,camera-flash@2 { - cell-index = <2>; - compatible = "qcom,camera-flash"; - flash-source = <&pmi632_flash0 &pmi632_flash1>; - torch-source = <&pmi632_torch0 &pmi632_torch1>; - switch-source = <&pmi632_switch0 &pmi632_switch0>; - status = "ok"; - }; - qcom,cam-res-mgr { compatible = "qcom,cam-res-mgr"; status = "ok"; + gpios-shared-pinctrl = <480>; + shared-pctrl-gpio-names = "gmsl"; + pinctrl-names = "gmsl_active", "gmsl_suspend"; + pinctrl-0 = <&cam_sensor_gmsl_active>; + pinctrl-1 = <&cam_sensor_gmsl_suspend>; + }; +}; + +&tlmm { + cam_sensor_gmsl_active: cam_sensor_active_gmsl { + /* RESET */ + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + bias-pull-up; + drive-strength = <2>; /* 2 MA */ + output-high; + }; + }; + + cam_sensor_gmsl_suspend: cam_sensor_suspend_gmsl { + /* RESET */ + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; }; }; &cam_cci0 { - actuator_rear: qcom,actuator0 { - cell-index = <0>; - compatible = "qcom,actuator"; - cci-master = <0>; - cam_vaf-supply = <&L5P>; - regulator-names = "cam_vaf"; - rgltr-cntrl-support; - rgltr-min-voltage = <2800000>; - rgltr-max-voltage = <2800000>; - rgltr-load-current = <100000>; - status = "ok"; - }; - actuator_rear_aux: qcom,actuator1 { - cell-index = <1>; - compatible = "qcom,actuator"; - cci-master = <1>; - cam_vaf-supply = <&L5P>; - regulator-names = "cam_vaf"; - rgltr-cntrl-support; - rgltr-min-voltage = <2800000>; - rgltr-max-voltage = <2800000>; - rgltr-load-current = <100000>; - status = "ok"; - }; - - eeprom_rear: qcom,eeprom0 { + /* CAM0A */ + qcom,cam-sensor0 { cell-index = <0>; - compatible = "qcom,eeprom"; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; cam_vio-supply = <&L7P>; - cam_vana-supply = <&L4P>; - cam_vdig-supply = <&L2P>; - cam_vaf-supply = <&L5P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_vaf"; + "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; - rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; - rgltr-load-current = <120000 80000 1200000 0 100000>; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 28 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /* CAM1 */ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L5P>; + cam_vdig-supply = <&L2P>; + + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 21 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /* CAM0B */ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear0_reset_active>; + &cam_sensor_active_rst2>; pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear0_reset_suspend>; + &cam_sensor_suspend_rst2>; gpios = <&tlmm 20 0>, - <&tlmm 18 0>; + <&tlmm 44 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; @@ -94,68 +168,95 @@ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "turbo"; - clock-rates = <19200000>; + clock-rates = <24000000>; }; - eeprom_rear_aux: qcom,eeprom1 { - cell-index = <1>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L3P>; - cam_vdig-supply = <&L1P>; - cam_vaf-supply = <&L5P>; + /* GMSL-1 */ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_vaf"; + regulator-names = "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; - rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; - rgltr-load-current = <120000 80000 1200000 0 100000>; + rgltr-min-voltage = <0>; + rgltr-max-voltage = <0>; + rgltr-load-current = <0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_rear1_reset_active>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_rear1_reset_suspend>; - gpios = <&tlmm 21 0>, - <&tlmm 19 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK1", - "CAM_RESET1"; + pinctrl-0 = <&cam_sensor_gmsl_active>; + pinctrl-1 = <&cam_sensor_gmsl_suspend>; + gpios = <&tlmm 81 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET2"; sensor-mode = <0>; - cci-master = <1>; + cci-master = <0>; status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; }; - eeprom_front: qcom,eeprom2 { - cell-index = <2>; - compatible = "qcom,eeprom"; + /* GMSL-2 */ + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0>; + rgltr-max-voltage = <0>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_gmsl_active>; + pinctrl-1 = <&cam_sensor_gmsl_suspend>; + gpios = <&tlmm 81 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + }; + + /* CAM2 */ + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; cam_vio-supply = <&L7P>; cam_vana-supply = <&L6P>; cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1050000 0>; - rgltr-max-voltage = <1800000 2800000 1050000 0>; - rgltr-load-current = <0 80000 105000 0>; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_front0_reset_active>; + &cam_sensor_active_rst5>; pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_front0_reset_suspend>; + &cam_sensor_suspend_rst5>; gpios = <&tlmm 27 0>, - <&tlmm 24 0>; + <&tlmm 19 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; @@ -169,233 +270,4 @@ clock-cntl-level = "turbo"; clock-rates = <24000000>; }; - - eeprom_rear_aux2: qcom,eeprom3 { - cell-index = <3>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L6P>; - cam_vdig-supply = <&L1P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1200000 0>; - rgltr-max-voltage = <1800000 2800000 1200000 0>; - rgltr-load-current = <120000 80000 1200000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk3_active - &cam_sensor_rear2_reset_active>; - pinctrl-1 = <&cam_sensor_mclk3_suspend - &cam_sensor_rear2_reset_suspend>; - gpios = <&tlmm 28 0>, - <&tlmm 65 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK3", - "CAM_RESET3"; - sensor-mode = <0>; - cci-master = <0>; - status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; - - /* Rear*/ - qcom,cam-sensor0 { - cell-index = <0>; - compatible = "qcom,cam-sensor"; - csiphy-sd-index = <0>; - sensor-position-roll = <270>; - sensor-position-pitch = <0>; - sensor-position-yaw = <180>; - actuator-src = <&actuator_rear>; - led-flash-src = <&led_flash_rear>; - eeprom-src = <&eeprom_rear>; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L4P>; - cam_vdig-supply = <&L2P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1050000 0>; - rgltr-max-voltage = <1800000 2800000 1050000 0>; - rgltr-load-current = <120000 80000 1200000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear0_reset_active>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear0_reset_suspend>; - gpios = <&tlmm 20 0>, - <&tlmm 18 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK0", - "CAM_RESET0"; - sensor-mode = <0>; - cci-master = <0>; - status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; - - /*Rear Aux*/ - qcom,cam-sensor1 { - cell-index = <1>; - compatible = "qcom,cam-sensor"; - csiphy-sd-index = <1>; - sensor-position-roll = <270>; - sensor-position-pitch = <0>; - sensor-position-yaw = <180>; - actuator-src = <&actuator_rear_aux>; - led-flash-src = <&led_flash_rear_aux>; - eeprom-src = <&eeprom_rear_aux>; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L3P>; - cam_vdig-supply = <&L1P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1200000 0>; - rgltr-max-voltage = <1800000 2800000 1200000 0>; - rgltr-load-current = <120000 80000 1200000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_rear1_reset_active>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_rear1_reset_suspend>; - gpios = <&tlmm 21 0>, - <&tlmm 19 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK1", - "CAM_RESET1"; - sensor-mode = <0>; - cci-master = <1>; - status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; - - /*Front*/ - qcom,cam-sensor2 { - cell-index = <2>; - compatible = "qcom,cam-sensor"; - csiphy-sd-index = <2>; - sensor-position-roll = <270>; - sensor-position-pitch = <0>; - sensor-position-yaw = <0>; - eeprom-src = <&eeprom_front>; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L6P>; - cam_vdig-supply = <&L2P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1050000 0>; - rgltr-max-voltage = <1800000 2800000 1050000 0>; - rgltr-load-current = <0 80000 105000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_front0_reset_active - &cam_sensor_csi_mux_oe_active - &cam_sensor_csi_mux_sel_active>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_front0_reset_suspend - &cam_sensor_csi_mux_oe_suspend - &cam_sensor_csi_mux_sel_suspend>; - gpios = <&tlmm 27 0>, - <&tlmm 24 0>, - <&tlmm 66 0>, - <&tlmm 67 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-custom2 = <3>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2", - "CAM_CSIMUX_OE0", - "CAM_CSIMUX_SEL0"; - sensor-mode = <0>; - cci-master = <1>; - status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <24000000>; - }; - - /*Rear Aux2*/ - qcom,cam-sensor3 { - cell-index = <3>; - compatible = "qcom,cam-sensor"; - csiphy-sd-index = <2>; - sensor-position-roll = <270>; - sensor-position-pitch = <0>; - sensor-position-yaw = <180>; - led-flash-src = <&led_flash_rear_aux2>; - eeprom-src = <&eeprom_rear_aux2>; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L6P>; - cam_vdig-supply = <&L1P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1200000 0>; - rgltr-max-voltage = <1800000 2800000 1200000 0>; - rgltr-load-current = <120000 80000 1200000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk3_active - &cam_sensor_rear2_reset_active - &cam_sensor_csi_mux_oe_active - &cam_sensor_csi_mux_sel_active>; - pinctrl-1 = <&cam_sensor_mclk3_suspend - &cam_sensor_rear2_reset_suspend - &cam_sensor_csi_mux_oe_suspend - &cam_sensor_csi_mux_sel_suspend>; - gpios = <&tlmm 28 0>, - <&tlmm 65 0>, - <&tlmm 66 0>, - <&tlmm 67 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-custom2 = <3>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK3", - "CAM_RESET3", - "CAM_CSIMUX_OE1", - "CAM_CSIMUX_SEL1"; - sensor-mode = <0>; - cci-master = <0>; - status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; }; diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 32e146f7d05c..c1d85c009b86 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -38,7 +38,6 @@ <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -69,7 +68,6 @@ <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -100,7 +98,6 @@ <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -277,13 +274,13 @@ reg = <0x5c11000 0x1000>, <0x5c13000 0x4000>; reg-cam-base = <0x11000 0x13000>; + cam_hw_fuse = ; interrupt-names = "cpas_camnoc"; interrupts = ; - camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/ + camnoc-axi-min-ib-bw = <3000000000>; regulator-names = "camss-vdd"; camss-vdd-supply = <&gcc_camss_top_gdsc>; clock-names = - "gcc_camss_ahb_clk", "gcc_camss_top_ahb_clk", "gcc_camss_top_ahb_clk_src", "gcc_camss_axi_clk", @@ -291,7 +288,6 @@ "gcc_camss_nrt_axi_clk", "gcc_camss_rt_axi_clk"; clocks = - <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, <&gcc GCC_CAMSS_AXI_CLK>, @@ -300,47 +296,37 @@ <&gcc GCC_CAMSS_RT_AXI_CLK>; src-clock-name = "gcc_camss_axi_clk_src"; clock-rates = - <0 0 0 0 0 0 0>, - <0 0 80000000 0 19200000 0 0>, - <0 0 80000000 0 150000000 0 0>, - <0 0 80000000 0 200000000 0 0>, - <0 0 80000000 0 300000000 0 0>, - <0 0 80000000 0 300000000 0 0>, - <0 0 80000000 0 300000000 0 0>; - clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", - "svs_l1", "nominal", "turbo"; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + <0 0 0 0 0 0>, + <0 19200000 0 19200000 0 0>, + <0 80000000 0 150000000 0 0>, + <0 80000000 0 200000000 0 0>, + <0 80000000 0 300000000 0 0>, + <0 80000000 0 300000000 0 0>, + <0 80000000 0 300000000 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; - qcom,msm-bus,name = "cam_ahb"; - qcom,msm-bus,num-cases = <7>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - , - , - , - , - ; - vdd-corners = ; + interconnect-names = "cam_ahb"; + interconnects =<&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_CAMERA_CFG>; + cam-ahb-num-cases = <7>; + cam-ahb-bw-KBps = + <0 0>, <0 133333>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; vdd-corner-ahb-mapping = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", @@ -360,19 +346,12 @@ node-name = "level2-rt0-rd-wr-sum"; traffic-merge-type = ; - qcom,axi-port-name = "cam_hf_0"; ib-bw-voting-needed; qcom,axi-port-mnoc { - qcom,msm-bus,name = - "cam_hf_0_mnoc"; - qcom,msm-bus-vector-dyn-vote; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; + interconnect-names = "cam_hf_0"; + interconnects = + <&mmrt_virt MASTER_CAMNOC_HF + &bimc SLAVE_EBI_CH0>; }; }; @@ -381,18 +360,11 @@ node-name = "level2-nrt0-rd-wr-sum"; traffic-merge-type = ; - qcom,axi-port-name = "cam_sf_0"; qcom,axi-port-mnoc { - qcom,msm-bus,name = - "cam_sf_0_mnoc"; - qcom,msm-bus-vector-dyn-vote; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; + interconnect-names = "cam_sf_0"; + interconnects = + <&mmnrt_virt MASTER_CAMNOC_SF + &bimc SLAVE_EBI_CH0>; }; }; }; @@ -594,8 +566,8 @@ compatible = "qcom,csid530"; reg-names = "csid", "top", "camnoc"; reg = <0x5c6e000 0x5000>, - <0x5c11000 0x1000>, - <0x5c13000 0x4000>; + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; reg-cam-base = <0x6e000 0x11000 0x13000>; interrupt-names = "csid0"; interrupts = ; @@ -622,7 +594,6 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -649,7 +620,6 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; cam_hw_pid = <4>; status = "ok"; }; @@ -659,8 +629,8 @@ compatible = "qcom,csid530"; reg-names = "csid", "top", "camnoc"; reg = <0x5c75000 0x5000>, - <0x5c11000 0x1000>, - <0x5c13000 0x4000>; + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; reg-cam-base = <0x75000 0x11000 0x13000>; interrupt-names = "csid1"; interrupts = ; @@ -687,7 +657,6 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -714,7 +683,6 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; cam_hw_pid = <5>; status = "ok"; }; @@ -724,8 +692,8 @@ compatible = "qcom,csid530"; reg-names = "csid", "top", "camnoc"; reg = <0x5c7c000 0x5000>, - <0x5c11000 0x1000>, - <0x5c13000 0x4000>; + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; reg-cam-base = <0x7c000 0x11000 0x13000>; interrupt-names = "csid2"; interrupts = ; @@ -752,7 +720,6 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -779,7 +746,6 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; cam_hw_pid = <6>; status = "ok"; }; @@ -814,7 +780,7 @@ cam_tfe_tpg1: qcom,tpg1@5c68000 { cell-index = <1>; compatible = "qcom,tpg101"; - reg-names = "tpg0", "top"; + reg-names = "tpg1", "top"; reg = <0x5c68000 0x400>, <0x5c11000 0x1000>; reg-cam-base = <0x68000 0x11000>; @@ -868,21 +834,22 @@ regulator-names = "camss"; camss-supply = <&gcc_camss_top_gdsc>; clock-names = + "ope_ahb_clk_src", "ope_ahb_clk", "ope_clk_src", "ope_clk"; clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK_SRC>, <&gcc GCC_CAMSS_OPE_AHB_CLK>, <&gcc GCC_CAMSS_OPE_CLK_SRC>, <&gcc GCC_CAMSS_OPE_CLK>; clock-rates = - <171428571 200000000 0>, - <171428571 266600000 0>, - <240000000 465000000 0>, - <240000000 580000000 0>; + <19200000 0 19200000 0>, + <171428571 0 200000000 0>, + <240000000 0 465000000 0>, + <240000000 0 580000000 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ope_clk_src"; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; }; diff --git a/qcs610-camera-sensor-idp.dtsi b/qcs610-camera-sensor-idp.dtsi new file mode 100644 index 000000000000..8ffa33dab049 --- /dev/null +++ b/qcs610-camera-sensor-idp.dtsi @@ -0,0 +1,63 @@ + +&soc { + camera_ldo: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "camera_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&pm6150l_gpios 3 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_dvdd_en>; + vin-supply = <&pm6150l_s8>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci { + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&pm6150l_l4>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 47 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <37125000>; + }; +}; diff --git a/qrb2210-rb1-camera-sensor-idp.dtsi b/qrb2210-rb1-camera-sensor-idp.dtsi deleted file mode 100644 index 225701809a35..000000000000 --- a/qrb2210-rb1-camera-sensor-idp.dtsi +++ /dev/null @@ -1,293 +0,0 @@ -#include -&soc { - qcom,cam-res-mgr { - compatible = "qcom,cam-res-mgr"; - status = "ok"; - }; -}; - -&cam_cci0 { - actuator_rear: qcom,actuator0 { - cell-index = <0>; - compatible = "qcom,actuator"; - cci-master = <0>; - cam_vaf-supply = <&L5P>; - regulator-names = "cam_vaf"; - rgltr-cntrl-support; - rgltr-min-voltage = <2800000>; - rgltr-max-voltage = <2800000>; - rgltr-load-current = <100000>; - status = "disabled"; - }; - - actuator_rear_aux: qcom,actuator1 { - cell-index = <1>; - compatible = "qcom,actuator"; - cci-master = <1>; - cam_vaf-supply = <&L5P>; - regulator-names = "cam_vaf"; - rgltr-cntrl-support; - rgltr-min-voltage = <2800000>; - rgltr-max-voltage = <2800000>; - rgltr-load-current = <100000>; - status = "disabled"; - }; - - eeprom_rear: qcom,eeprom0 { - cell-index = <0>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L4P>; - cam_vdig-supply = <&L2P>; - cam_vaf-supply = <&L5P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_vaf"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; - rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; - rgltr-load-current = <120000 80000 1200000 0 100000>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear0_reset_active>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear0_reset_suspend>; - gpios = <&tlmm 20 0>, - <&tlmm 18 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK0", - "CAM_RESET0"; - sensor-mode = <0>; - cci-master = <0>; - status = "disabled"; - clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; - - eeprom_rear_aux: qcom,eeprom1 { - cell-index = <1>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L3P>; - cam_vdig-supply = <&L1P>; - cam_vaf-supply = <&L5P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_vaf"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; - rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; - rgltr-load-current = <120000 80000 1200000 0 100000>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_rear1_reset_active>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_rear1_reset_suspend>; - gpios = <&tlmm 21 0>, - <&tlmm 19 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK1", - "CAM_RESET1"; - sensor-mode = <0>; - cci-master = <1>; - status = "disabled"; - clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; - - eeprom_front: qcom,eeprom2 { - cell-index = <2>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L6P>; - cam_vdig-supply = <&L2P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; - rgltr-load-current = <0 80000 105000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_front0_reset_active>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_front0_reset_suspend>; - gpios = <&tlmm 27 0>, - <&tlmm 24 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2"; - sensor-mode = <0>; - cci-master = <1>; - status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <24000000>; - }; - - /* Rear*/ - qcom,cam-sensor0 { - cell-index = <0>; - compatible = "qcom,cam-sensor"; - csiphy-sd-index = <0>; - sensor-position-roll = <270>; - sensor-position-pitch = <0>; - sensor-position-yaw = <180>; - actuator-src = <&actuator_rear>; - eeprom-src = <&eeprom_rear>; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L4P>; - cam_vdig-supply = <&L2P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; - rgltr-load-current = <120000 80000 1200000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear0_reset_active>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear0_reset_suspend>; - gpios = <&tlmm 20 0>, - <&tlmm 18 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK0", - "CAM_RESET0"; - sensor-mode = <0>; - cci-master = <0>; - status = "disabled"; - clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; - - /*Rear Aux*/ - qcom,cam-sensor1 { - cell-index = <1>; - compatible = "qcom,cam-sensor"; - csiphy-sd-index = <1>; - sensor-position-roll = <270>; - sensor-position-pitch = <0>; - sensor-position-yaw = <180>; - actuator-src = <&actuator_rear_aux>; - eeprom-src = <&eeprom_rear_aux>; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L3P>; - cam_vdig-supply = <&L1P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1200000 0>; - rgltr-max-voltage = <1800000 2800000 1200000 0>; - rgltr-load-current = <120000 80000 1200000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_rear1_reset_active - &cam_sensor_csi_mux_oe_active - &cam_sensor_csi_mux_sel_active>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_rear1_reset_suspend - &cam_sensor_csi_mux_oe_suspend - &cam_sensor_csi_mux_sel_suspend>; - gpios = <&tlmm 21 0>, - <&tlmm 19 0>, - <&tlmm 113 0>, - <&tlmm 114 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-custom2 = <3>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK1", - "CAM_RESET1", - "CAM_CSIMUX_OE0", - "CAM_CSIMUX_SEL0"; - sensor-mode = <0>; - cci-master = <1>; - status = "disabled"; - clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; - - /*Front*/ - qcom,cam-sensor2 { - cell-index = <2>; - compatible = "qcom,cam-sensor"; - csiphy-sd-index = <1>; - sensor-position-roll = <270>; - sensor-position-pitch = <0>; - sensor-position-yaw = <0>; - eeprom-src = <&eeprom_front>; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L6P>; - cam_vdig-supply = <&L2P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; - rgltr-load-current = <0 80000 105000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_front0_reset_active - &cam_sensor_csi_mux_oe_active - &cam_sensor_csi_mux_sel_active>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_front0_reset_suspend - &cam_sensor_csi_mux_oe_suspend - &cam_sensor_csi_mux_sel_suspend>; - gpios = <&tlmm 27 0>, - <&tlmm 24 0>, - <&tlmm 113 0>, - <&tlmm 114 0>; - gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-custom2 = <3>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2", - "CAM_CSIMUX_OE0", - "CAM_CSIMUX_SEL0"; - sensor-mode = <0>; - cci-master = <1>; - status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <24000000>; - }; -}; diff --git a/qrb2210-rb1-camera.dtsi b/qrb2210-rb1-camera.dtsi deleted file mode 100644 index 97eeb826a117..000000000000 --- a/qrb2210-rb1-camera.dtsi +++ /dev/null @@ -1,747 +0,0 @@ -#include - -&soc { - qcom,cam-req-mgr { - compatible = "qcom,cam-req-mgr"; - status = "ok"; - }; - - qcom,cam-sync { - compatible = "qcom,cam-sync"; - status = "ok"; - }; - - cam_csiphy0: qcom,csiphy0 { - cell-index = <0>; - compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; - reg = <0x05C52000 0x1000>; - reg-names = "csiphy"; - reg-cam-base = <0x52000>; - interrupts = ; - interrupt-names = "csiphy"; - regulator-names = "gdscr"; - gdscr-supply = <&gcc_camss_top_gdsc>; - csi-vdd-voltage = <1200000>; - mipi-csi-vdd-supply = <&L5A>; - clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, - <&gcc GCC_CAMSS_CPHY_0_CLK>, - <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, - <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>; - clock-names = "cphy_rx_clk_src", - "csiphy0_clk", - "csi0phytimer_clk_src", - "csi0phytimer_clk"; - src-clock-name = "csi0phytimer_clk_src"; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - clock-rates = - <19200000 0 19200000 0>, - <341330000 0 200000000 0>, - <341330000 0 200000000 0>, - <384000000 0 268800000 0>; - status = "ok"; - }; - - cam_csiphy1: qcom,csiphy1 { - cell-index = <1>; - compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; - reg = <0x05C53000 0x1000>; - reg-names = "csiphy"; - reg-cam-base = <0x53000>; - interrupts = ; - interrupt-names = "csiphy"; - regulator-names = "gdscr"; - gdscr-supply = <&gcc_camss_top_gdsc>; - csi-vdd-voltage = <1200000>; - mipi-csi-vdd-supply = <&L5A>; - clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, - <&gcc GCC_CAMSS_CPHY_1_CLK>, - <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, - <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>; - clock-names = "cphy_rx_clk_src", - "csiphy1_clk", - "csi1phytimer_clk_src", - "csi1phytimer_clk"; - src-clock-name = "csi1phytimer_clk_src"; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - clock-rates = - <19200000 0 19200000 0>, - <341330000 0 200000000 0>, - <341330000 0 200000000 0>, - <384000000 0 268800000 0>; - status = "ok"; - }; - - cam_cci0: qcom,cci0 { - cell-index = <0>; - compatible = "qcom,cci", "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x05C1B000 0x1000>; - reg-names = "cci"; - reg-cam-base = <0x1B000>; - interrupt-names = "cci"; - interrupts = ; - status = "ok"; - gdscr-supply = <&gcc_camss_top_gdsc>; - regulator-names = "gdscr"; - clocks = <&gcc GCC_CAMSS_CCI_0_CLK>, - <&gcc GCC_CAMSS_CCI_CLK_SRC>; - clock-names = "cci_0_clk", - "cci_0_clk_src"; - src-clock-name = "cci_0_clk_src"; - clock-cntl-level = "svs"; - clock-rates = <0 37500000>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cci0_active &cci1_active>; - pinctrl-1 = <&cci0_suspend &cci1_suspend>; - gpios = <&tlmm 22 0>, - <&tlmm 23 0>, - <&tlmm 29 0>, - <&tlmm 30 0>; - gpio-req-tbl-num = <0 1 2 3>; - gpio-req-tbl-flags = <1 1 1 1>; - gpio-req-tbl-label = "CCI_I2C_DATA0", - "CCI_I2C_CLK0", - "CCI_I2C_DATA1", - "CCI_I2C_CLK1"; - - i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { - hw-thigh = <201>; - hw-tlow = <174>; - hw-tsu-sto = <204>; - hw-tsu-sta = <231>; - hw-thd-dat = <22>; - hw-thd-sta = <162>; - hw-tbuf = <227>; - hw-scl-stretch-en = <0>; - hw-trdhld = <6>; - hw-tsp = <3>; - cci-clk-src = <37500000>; - status = "ok"; - }; - - i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { - hw-thigh = <38>; - hw-tlow = <56>; - hw-tsu-sto = <40>; - hw-tsu-sta = <40>; - hw-thd-dat = <22>; - hw-thd-sta = <35>; - hw-tbuf = <62>; - hw-scl-stretch-en = <0>; - hw-trdhld = <6>; - hw-tsp = <3>; - cci-clk-src = <37500000>; - status = "ok"; - }; - - i2c_freq_custom_cci0: qcom,i2c_custom_mode { - hw-thigh = <38>; - hw-tlow = <56>; - hw-tsu-sto = <40>; - hw-tsu-sta = <40>; - hw-thd-dat = <22>; - hw-thd-sta = <35>; - hw-tbuf = <62>; - hw-scl-stretch-en = <1>; - hw-trdhld = <6>; - hw-tsp = <3>; - cci-clk-src = <37500000>; - status = "ok"; - }; - - i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { - hw-thigh = <16>; - hw-tlow = <22>; - hw-tsu-sto = <17>; - hw-tsu-sta = <18>; - hw-thd-dat = <16>; - hw-thd-sta = <15>; - hw-tbuf = <24>; - hw-scl-stretch-en = <0>; - hw-trdhld = <3>; - hw-tsp = <3>; - cci-clk-src = <37500000>; - status = "ok"; - }; - }; - - qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu", "simple-bus"; - status = "ok"; - - msm_cam_smmu_tfe { - compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x400 0x000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; - cam-smmu-label = "tfe"; - tfe_iova_mem_map: iova-mem-map { - /* IO region is approximately 3.4 GB */ - iova-mem-region-io { - iova-region-name = "io"; - iova-region-start = <0x7400000>; - iova-region-len = <0xd8c00000>; - iova-region-id = <0x3>; - status = "ok"; - }; - }; - }; - - msm_cam_smmu_ope { - compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x820 0x000>, - <&apps_smmu 0x840 0x000>; - qcom,iommu-faults = "non-fatal"; - multiple-client-devices; - qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; - cam-smmu-label = "ope", "ope-cdm"; - ope_iova_mem_map: iova-mem-map { - /* IO region is approximately 3.4 GB */ - iova-mem-region-io { - iova-region-name = "io"; - iova-region-start = <0x7400000>; - iova-region-len = <0xd8c00000>; - iova-region-id = <0x3>; - status = "ok"; - }; - }; - }; - - msm_cam_smmu_cpas_cdm { - compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x800 0x000>; - cam-smmu-label = "cpas-cdm"; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; - cpas_cdm_iova_mem_map: iova-mem-map { - iova-mem-region-io { - /* IO region is approximately 3.4 GB */ - iova-region-name = "io"; - iova-region-start = <0x7400000>; - iova-region-len = <0xd8c00000>; - iova-region-id = <0x3>; - status = "ok"; - }; - }; - }; - - msm_cam_smmu_secure { - compatible = "qcom,msm-cam-smmu-cb"; - cam-smmu-label = "cam-secure"; - qcom,secure-cb; - }; - }; - - qcom,cam-cpas@5c11000 { - cell-index = <0>; - compatible = "qcom,cam-cpas", "simple-bus"; - label = "cpas"; - arch-compat = "cpas_top"; - status = "ok"; - reg-names = "cam_cpas_top", "cam_camnoc"; - reg = <0x5c11000 0x1000>, - <0x5c13000 0x4000>; - reg-cam-base = <0x11000 0x13000>; - cam_hw_fuse = ; - interrupt-names = "cpas_camnoc"; - interrupts = ; - camnoc-axi-min-ib-bw = <3000000000>; - regulator-names = "camss-vdd"; - camss-vdd-supply = <&gcc_camss_top_gdsc>; - clock-names = - "gcc_camss_ahb_clk", - "gcc_camss_top_ahb_clk", - "gcc_camss_top_ahb_clk_src", - "gcc_camss_axi_clk", - "gcc_camss_axi_clk_src", - "gcc_camss_nrt_axi_clk", - "gcc_camss_rt_axi_clk"; - clocks = - <&gcc GCC_CAMERA_AHB_CLK>, - <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, - <&gcc GCC_CAMSS_AXI_CLK>, - <&gcc GCC_CAMSS_AXI_CLK_SRC>, - <&gcc GCC_CAMSS_NRT_AXI_CLK>, - <&gcc GCC_CAMSS_RT_AXI_CLK>; - src-clock-name = "gcc_camss_axi_clk_src"; - clock-rates = - <0 0 0 0 0 0 0>, - <0 0 19200000 0 19200000 0 0>, - <0 0 80000000 0 150000000 0 0>, - <0 0 80000000 0 200000000 0 0>, - <0 0 80000000 0 300000000 0 0>, - <0 0 80000000 0 300000000 0 0>, - <0 0 80000000 0 300000000 0 0>; - // clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", - clock-cntl-level = "suspend", "lowsvs", "svs", - "svs_l1", "nominal", "nominal_l1", "turbo"; - // qcom,cx-ipeak-gpu-limit = <921600000>; - control-camnoc-axi-clk; - camnoc-bus-width = <32>; - camnoc-axi-clk-bw-margin-perc = <20>; - interconnect-names = "cam_ahb"; - interconnects =<&bimc MASTER_AMPSS_M0 - &config_noc SLAVE_CAMERA_CFG>; - cam-ahb-num-cases = <7>; - cam-ahb-bw-KBps = - <0 0>, <0 133333>, <0 150000>, <0 150000>, - <0 300000>, <0 300000>, <0 300000>; - vdd-corners = ; - vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", - "lowsvs", "lowsvs", "svs", "svs_l1", "svs_l1", - "svs_l1", "nominal", "nominal", "nominal", - "turbo", "turbo"; - client-id-based; - client-names = - "csiphy0", "csiphy1", "cci0", - "csid0", "csid1", "tfe0", - "tfe1", "ope0", "cam-cdm-intf0", - "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1"; - - camera-bus-nodes { - level2-nodes { - level-index = <2>; - level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum { - cell-index = <0>; - node-name = "level2-rt0-rd-wr-sum"; - traffic-merge-type = - ; - ib-bw-voting-needed; - qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0"; - interconnects = - <&mmrt_virt MASTER_CAMNOC_HF - &bimc SLAVE_EBI_CH0>; - }; - }; - - level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum { - cell-index = <1>; - node-name = "level2-nrt0-rd-wr-sum"; - traffic-merge-type = - ; - qcom,axi-port-mnoc { - interconnect-names = "cam_sf_0"; - interconnects = - <&mmnrt_virt MASTER_CAMNOC_SF - &bimc SLAVE_EBI_CH0>; - }; - }; - }; - - level1-nodes { - level-index = <1>; - camnoc-max-needed; - level1_rt0_wr: level1-rt0-wr { - cell-index = <2>; - node-name = "level1-rt0-wr"; - parent-node = <&level2_rt0_rd_wr_sum>; - traffic-merge-type = - ; - }; - - level1_nrt0_rd_wr: level1-nrt0-rd-wr { - cell-index = <3>; - node-name = "level1-nrt0-rd-wr"; - parent-node = <&level2_nrt0_rd_wr_sum>; - traffic-merge-type = - ; - }; - }; - - level0-nodes { - level-index = <0>; - ope0_all_wr: ope0-all-wr { - cell-index = <4>; - node-name = "ope0-all-wr"; - client-name = "ope0"; - traffic-data = ; - traffic-transaction-type = - ; - constituent-paths = - ; - parent-node = <&level1_nrt0_rd_wr>; - }; - - ope0_all_rd: ope0-all-rd { - cell-index = <5>; - node-name = "ope0-all-rd"; - client-name = "ope0"; - traffic-data = ; - traffic-transaction-type = - ; - constituent-paths = - ; - parent-node = <&level1_nrt0_rd_wr>; - }; - - tfe0_all_wr: tfe0-all-wr { - cell-index = <6>; - node-name = "tfe0-all-wr"; - client-name = "tfe0"; - traffic-data = ; - traffic-transaction-type = - ; - constituent-paths = - ; - parent-node = <&level1_rt0_wr>; - }; - - tfe1_all_wr: tfe1-all-wr { - cell-index = <7>; - node-name = "tfe1-all-wr"; - client-name = "tfe1"; - traffic-data = ; - traffic-transaction-type = - ; - constituent-paths = - ; - parent-node = <&level1_rt0_wr>; - }; - - cpas_cdm0_all_rd: cpas-cdm0-all-rd { - cell-index = <9>; - node-name = "cpas-cdm0-all-rd"; - client-name = "cpas-cdm0"; - traffic-data = ; - traffic-transaction-type = - ; - parent-node = <&level1_nrt0_rd_wr>; - }; - - ope_cdm0_all_rd: ope-cdm0-all-rd { - cell-index = <10>; - node-name = "ope-cdm0-all-rd"; - client-name = "ope-cdm0"; - traffic-data = ; - traffic-transaction-type = - ; - parent-node = <&level1_nrt0_rd_wr>; - }; - }; - }; - }; - - qcom,cam-cdm-intf { - compatible = "qcom,cam-cdm-intf"; - cell-index = <0>; - label = "cam-cdm-intf"; - num-hw-cdm = <2>; - cdm-client-names = "vfe"; - status = "ok"; - }; - - cam_cpas_cdm: qcom,cpas-cdm0@5c23000 { - cell-index = <0>; - compatible = "qcom,cam-cpas-cdm2_0"; - label = "cpas-cdm"; - reg = <0x5c23000 0x400>; - reg-names = "cpas-cdm0"; - reg-cam-base = <0x23000>; - interrupts = ; - interrupt-names = "cpas-cdm0"; - regulator-names = "camss"; - camss-supply = <&gcc_camss_top_gdsc>; - clock-names = "cam_cc_cpas_top_ahb_clk"; - clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>; - clock-rates = <0>; - clock-cntl-level = "svs"; - cdm-client-names = "tfe0", "tfe1"; - config-fifo; - fifo-depths = <64 64 64 64>; - status = "ok"; - }; - - cam_ope_cdm: qcom,ope-cdm0@5c42000 { - cell-index = <0>; - compatible = "qcom,cam-ope-cdm2_1"; - label = "ope-cdm"; - reg = <0x5c42000 0x400>; - reg-names = "ope-cdm0"; - reg-cam-base = <0x42000>; - interrupts = ; - interrupt-names = "ope-cdm0"; - regulator-names = "camss"; - camss-supply = <&gcc_camss_top_gdsc>; - clock-names = - "ope_ahb_clk", - "ope_clk_src", - "ope_clk"; - clocks = - <&gcc GCC_CAMSS_OPE_AHB_CLK>, - <&gcc GCC_CAMSS_OPE_CLK_SRC>, - <&gcc GCC_CAMSS_OPE_CLK>; - clock-rates = <0 0 0>, - <0 0 0>, - <0 0 0>, - <0 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - cdm-client-names = "ope"; - config-fifo; - fifo-depths = <64 64 64 64>; - status = "ok"; - }; - - qcom,cam-isp { - compatible = "qcom,cam-isp"; - arch-compat = "tfe"; - status = "ok"; - }; - - cam_tfe_csid0: qcom,tfe_csid0@5c6e000 { - cell-index = <0>; - compatible = "qcom,csid530"; - reg-names = "csid", "top", "camnoc"; - reg = <0x5c6e000 0x1000>, - <0x5c11000 0x1000>, - <0x5c13000 0x4000>; - reg-cam-base = <0x6e000 0x11000 0x13000>; - interrupt-names = "csid0"; - interrupts = ; - regulator-names = "camss"; - camss-supply = <&gcc_camss_top_gdsc>; - clock-names = - "tfe_csid_clk_src", - "tfe_csid_clk", - "cphy_rx_clk_src", - "tfe_cphy_rx_clk", - "tfe_clk_src", - "tfe_clk"; - clocks = - <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, - <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, - <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CLK>; - clock-rates = - <240000000 0 0 0 256000000 0>, - <384000000 0 0 0 460800000 0>, - <426400000 0 0 0 576000000 0>; - clock-cntl-level = "svs", "svs_l1", "turbo"; - src-clock-name = "tfe_csid_clk_src"; - clock-control-debugfs = "true"; - status = "ok"; - }; - - cam_tfe0: qcom,tfe0@5c6e000 { - cell-index = <0>; - compatible = "qcom,tfe530"; - reg-names = "tfe0"; - reg = <0x5c6e000 0x5000>; - reg-cam-base = <0x6e000>; - interrupt-names = "tfe0"; - interrupts = ; - regulator-names = "camss"; - camss-supply = <&gcc_camss_top_gdsc>; - clock-names = - "tfe_clk_src", - "tfe_clk"; - clocks = - <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CLK>; - clock-rates = - <256000000 0>, - <460800000 0>, - <576000000 0>; - clock-cntl-level = "svs", "svs_l1", "turbo"; - src-clock-name = "tfe_clk_src"; - clock-control-debugfs = "true"; - cam_hw_pid = <4>; - status = "ok"; - }; - - cam_tfe_csid1: qcom,tfe_csid1@5c75000 { - cell-index = <1>; - compatible = "qcom,csid530"; - reg-names = "csid", "top", "camnoc"; - reg = <0x5c75000 0x1000>, - <0x5c11000 0x1000>, - <0x5c13000 0x4000>; - reg-cam-base = <0x75000 0x11000 0x13000>; - interrupt-names = "csid1"; - interrupts = ; - regulator-names = "camss"; - camss-supply = <&gcc_camss_top_gdsc>; - clock-names = - "tfe_csid_clk_src", - "tfe_csid_clk", - "cphy_rx_clk_src", - "tfe_cphy_rx_clk", - "tfe_clk_src", - "tfe_clk"; - clocks = - <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, - <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, - <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CLK>; - clock-rates = - <240000000 0 240000000 0 256000000 0>, - <384000000 0 341333333 0 460800000 0>, - <426400000 0 384000000 0 576000000 0>; - clock-cntl-level = "svs", "svs_l1", "turbo"; - src-clock-name = "tfe_csid_clk_src"; - clock-control-debugfs = "true"; - status = "ok"; - }; - - cam_tfe1: qcom,tfe1@5c75000 { - cell-index = <1>; - compatible = "qcom,tfe530"; - reg-names = "tfe1"; - reg = <0x5c75000 0x5000>; - reg-cam-base = <0x75000>; - interrupt-names = "tfe1"; - interrupts = ; - regulator-names = "camss"; - camss-supply = <&gcc_camss_top_gdsc>; - clock-names = - "tfe_clk_src", - "tfe_clk"; - clocks = - <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CLK>; - clock-rates = - <256000000 0>, - <460800000 0>, - <576000000 0>; - clock-cntl-level = "svs", "svs_l1", "turbo"; - src-clock-name = "tfe_clk_src"; - clock-control-debugfs = "true"; - cam_hw_pid = <5>; - status = "ok"; - }; - - cam_tfe_tpg0: qcom,tpg0@5c66000 { - cell-index = <0>; - compatible = "qcom,tpg101"; - reg-names = "tpg0", "top"; - reg = <0x5c66000 0x400>, - <0x5c11000 0x1000>; - reg-cam-base = <0x66000 0x11000>; - regulator-names = "camss"; - camss-supply = <&gcc_camss_top_gdsc>; - clock-names = - "cphy_rx_clk_src", - "tfe_0_cphy_rx_clk", - "gcc_camss_cphy_0_clk"; - clocks = - <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, - <&gcc GCC_CAMSS_CPHY_0_CLK>; - clock-rates = - <240000000 0 0>, - <341333333 0 0>, - <384000000 0 0>; - clock-cntl-level = "svs", "svs_l1", "turbo"; - src-clock-name = "cphy_rx_clk_src"; - clock-control-debugfs = "false"; - status = "ok"; - }; - - cam_tfe_tpg1: qcom,tpg1@5c68000 { - cell-index = <1>; - compatible = "qcom,tpg101"; - reg-names = "tpg1", "top"; - reg = <0x5c68000 0x400>, - <0x5c11000 0x1000>; - reg-cam-base = <0x68000 0x11000>; - regulator-names = "camss"; - camss-supply = <&gcc_camss_top_gdsc>; - clock-names = - "cphy_rx_clk_src", - "tfe_1_cphy_rx_clk", - "gcc_camss_cphy_1_clk"; - clocks = - <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, - <&gcc GCC_CAMSS_CPHY_1_CLK>; - clock-rates = - <240000000 0 0>, - <341333333 0 0>, - <384000000 0 0>; - clock-cntl-level = "svs", "svs_l1", "turbo"; - src-clock-name = "cphy_rx_clk_src"; - clock-control-debugfs = "false"; - status = "ok"; - }; - - qcom,cam-ope { - compatible = "qcom,cam-ope"; - compat-hw-name = "qcom,ope"; - num-ope = <1>; - status = "ok"; - }; - - ope: qcom,ope@0x5c42000 { - cell-index = <0>; - compatible = "qcom,ope"; - reg = - <0x5c42000 0x400>, - <0x5c42400 0x200>, - <0x5c42600 0x200>, - <0x5c42800 0x4400>, - <0x5c46c00 0x190>, - <0x5c46d90 0xA00>; - reg-names = - "ope_cdm", - "ope_top", - "ope_qos", - "ope_pp", - "ope_bus_rd", - "ope_bus_wr"; - reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>; - interrupts = ; - interrupt-names = "ope"; - regulator-names = "camss"; - camss-supply = <&gcc_camss_top_gdsc>; - clock-names = - "ope_ahb_clk_src", - "ope_ahb_clk", - "ope_clk_src", - "ope_clk"; - clocks = - <&gcc GCC_CAMSS_OPE_AHB_CLK_SRC>, - <&gcc GCC_CAMSS_OPE_AHB_CLK>, - <&gcc GCC_CAMSS_OPE_CLK_SRC>, - <&gcc GCC_CAMSS_OPE_CLK>; - clock-rates = - <19200000 0 19200000 0>, - <171428571 0 200000000 0>, - <240000000 0 465000000 0>, - <240000000 0 580000000 0>; - clock-cntl-level = "lowsvs", "svs", "nominal", "turbo"; - src-clock-name = "ope_clk_src"; - status = "ok"; - }; -}; diff --git a/scuba-camera-sensor-idp.dtsi b/scuba-camera-sensor-idp.dtsi index 6c7655b20cd8..8aac96ba7f9e 100644 --- a/scuba-camera-sensor-idp.dtsi +++ b/scuba-camera-sensor-idp.dtsi @@ -1,211 +1,93 @@ #include &soc { - led_flash_rear: qcom,camera-flash@0 { - cell-index = <0>; - compatible = "qcom,camera-flash"; - flash-source = <&pm2250_flash0>; - torch-source = <&pm2250_torch0>; - switch-source = <&pm2250_switch0>; - status = "ok"; - }; - - led_flash_rear_aux: qcom,camera-flash@1 { - cell-index = <1>; - compatible = "qcom,camera-flash"; - flash-source = <&pm2250_flash0>; - torch-source = <&pm2250_torch0>; - switch-source = <&pm2250_switch0>; - status = "ok"; - }; - qcom,cam-res-mgr { compatible = "qcom,cam-res-mgr"; status = "ok"; + gpios-shared-pinctrl = <466>; + shared-pctrl-gpio-names = "gmsl"; + pinctrl-names = "gmsl_active", "gmsl_suspend"; + pinctrl-0 = <&cam_sensor_gmsl_active>; + pinctrl-1 = <&cam_sensor_gmsl_suspend>; + }; +}; + +&tlmm { + cam_sensor_gmsl_active: cam_sensor_active_gmsl { + /* RESET */ + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + bias-pull-up; + drive-strength = <2>; /* 2 MA */ + output-high; + }; + }; + + cam_sensor_gmsl_suspend: cam_sensor_suspend_gmsl { + /* RESET */ + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; }; }; &cam_cci0 { - actuator_rear: qcom,actuator0 { + + /* CAM0A */ + qcom,cam-sensor0 { cell-index = <0>; - compatible = "qcom,actuator"; - cci-master = <0>; - cam_vaf-supply = <&L5P>; - regulator-names = "cam_vaf"; - rgltr-cntrl-support; - rgltr-min-voltage = <2800000>; - rgltr-max-voltage = <2800000>; - rgltr-load-current = <100000>; - status = "ok"; - }; - - actuator_rear_aux: qcom,actuator1 { - cell-index = <1>; - compatible = "qcom,actuator"; - cci-master = <1>; - cam_vaf-supply = <&L5P>; - regulator-names = "cam_vaf"; - rgltr-cntrl-support; - rgltr-min-voltage = <2800000>; - rgltr-max-voltage = <2800000>; - rgltr-load-current = <100000>; - status = "ok"; - }; - - eeprom_rear: qcom,eeprom0 { - cell-index = <0>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L4P>; - cam_vdig-supply = <&L2P>; - cam_vaf-supply = <&L5P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_vaf"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; - rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; - rgltr-load-current = <120000 80000 1200000 0 100000>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear0_reset_active>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear0_reset_suspend>; - gpios = <&tlmm 20 0>, - <&tlmm 18 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK0", - "CAM_RESET0"; - sensor-mode = <0>; - cci-master = <0>; - status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; - - eeprom_rear_aux: qcom,eeprom1 { - cell-index = <1>; - compatible = "qcom,eeprom"; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; cam_vio-supply = <&L7P>; cam_vana-supply = <&L3P>; cam_vdig-supply = <&L1P>; - cam_vaf-supply = <&L5P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_vaf"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; - rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; - rgltr-load-current = <120000 80000 1200000 0 100000>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_rear1_reset_active>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_rear1_reset_suspend>; - gpios = <&tlmm 21 0>, - <&tlmm 19 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK1", - "CAM_RESET1"; - sensor-mode = <0>; - cci-master = <1>; - status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; - eeprom_front: qcom,eeprom2 { - cell-index = <2>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L6P>; - cam_vdig-supply = <&L2P>; cam_clk-supply = <&gcc_camss_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; - rgltr-load-current = <0 80000 105000 0>; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_front0_reset_active>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_front0_reset_suspend>; - gpios = <&tlmm 27 0>, - <&tlmm 24 0>; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 28 0>, + <&tlmm 18 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2"; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET0"; sensor-mode = <0>; cci-master = <1>; status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; clock-names = "cam_clk"; clock-cntl-level = "turbo"; clock-rates = <24000000>; }; - /* Rear*/ - qcom,cam-sensor0 { - cell-index = <0>; - compatible = "qcom,cam-sensor"; - csiphy-sd-index = <0>; - sensor-position-roll = <270>; - sensor-position-pitch = <0>; - sensor-position-yaw = <180>; - actuator-src = <&actuator_rear>; - led-flash-src = <&led_flash_rear>; - eeprom-src = <&eeprom_rear>; - cam_vio-supply = <&L7P>; - cam_vana-supply = <&L4P>; - cam_vdig-supply = <&L2P>; - cam_clk-supply = <&gcc_camss_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <1800000 2800000 1050000 0>; - rgltr-max-voltage = <1800000 2800000 1050000 0>; - rgltr-load-current = <120000 80000 1200000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear0_reset_active>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear0_reset_suspend>; - gpios = <&tlmm 20 0>, - <&tlmm 18 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK0", - "CAM_RESET0"; - sensor-mode = <0>; - cci-master = <0>; - status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <19200000>; - }; - - /*Rear Aux*/ + /* CAM1 */ qcom,cam-sensor1 { cell-index = <1>; compatible = "qcom,cam-sensor"; @@ -213,12 +95,10 @@ sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; - actuator-src = <&actuator_rear_aux>; - led-flash-src = <&led_flash_rear_aux>; - eeprom-src = <&eeprom_rear_aux>; cam_vio-supply = <&L7P>; - cam_vana-supply = <&L3P>; - cam_vdig-supply = <&L1P>; + cam_vana-supply = <&L5P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; @@ -230,84 +110,123 @@ gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_rear1_reset_active - &cam_sensor_csi_mux_oe_active - &cam_sensor_csi_mux_sel_active>; + &cam_sensor_active_rst1>; pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_rear1_reset_suspend - &cam_sensor_csi_mux_oe_suspend - &cam_sensor_csi_mux_sel_suspend>; + &cam_sensor_suspend_rst1>; gpios = <&tlmm 21 0>, - <&tlmm 19 0>, - <&tlmm 113 0>, - <&tlmm 114 0>; + <&tlmm 24 0>; gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-custom2 = <3>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK1", - "CAM_RESET1", - "CAM_CSIMUX_OE0", - "CAM_CSIMUX_SEL0"; + "CAM_RESET1"; sensor-mode = <0>; - cci-master = <1>; + cci-master = <0>; status = "ok"; clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; clock-names = "cam_clk"; clock-cntl-level = "turbo"; - clock-rates = <19200000>; + clock-rates = <24000000>; }; - /*Front*/ + /* CAM0B */ qcom,cam-sensor2 { cell-index = <2>; compatible = "qcom,cam-sensor"; - csiphy-sd-index = <1>; + csiphy-sd-index = <0>; sensor-position-roll = <270>; sensor-position-pitch = <0>; - sensor-position-yaw = <0>; - eeprom-src = <&eeprom_front>; + sensor-position-yaw = <180>; cam_vio-supply = <&L7P>; - cam_vana-supply = <&L6P>; - cam_vdig-supply = <&L2P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; - rgltr-load-current = <0 80000 105000 0>; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_front0_reset_active - &cam_sensor_csi_mux_oe_active - &cam_sensor_csi_mux_sel_active>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_front0_reset_suspend - &cam_sensor_csi_mux_oe_suspend - &cam_sensor_csi_mux_sel_suspend>; - gpios = <&tlmm 27 0>, - <&tlmm 24 0>, - <&tlmm 113 0>, - <&tlmm 114 0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 20 0>, + <&tlmm 44 0>; gpio-reset = <1>; - gpio-custom1 = <2>; - gpio-custom2 = <3>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2", - "CAM_CSIMUX_OE0", - "CAM_CSIMUX_SEL0"; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; sensor-mode = <0>; - cci-master = <1>; + cci-master = <0>; status = "ok"; - clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "turbo"; clock-rates = <24000000>; }; + + /* GMSL-1 */ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0>; + rgltr-max-voltage = <0>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_gmsl_active>; + pinctrl-1 = <&cam_sensor_gmsl_suspend>; + gpios = <&tlmm 81 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + }; + + /* GMSL-2 */ + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0>; + rgltr-max-voltage = <0>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_gmsl_active>; + pinctrl-1 = <&cam_sensor_gmsl_suspend>; + gpios = <&tlmm 81 0>; + gpio-reset = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + }; + }; diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi index 8fd5fc199820..c020e4fcaa82 100644 --- a/scuba-camera.dtsi +++ b/scuba-camera.dtsi @@ -6,6 +6,11 @@ status = "ok"; }; + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + cam_csiphy0: qcom,csiphy0 { cell-index = <0>; compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; @@ -68,7 +73,7 @@ cam_cci0: qcom,cci0 { cell-index = <0>; - compatible = "qcom,cci"; + compatible = "qcom,cci", "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg = <0x05C1B000 0x1000>; @@ -162,7 +167,7 @@ }; qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu"; + compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; msm_cam_smmu_tfe { @@ -190,7 +195,7 @@ qcom,iommu-faults = "non-fatal"; multiple-client-devices; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; - cam-smmu-label = "ope", "ope-cdm0"; + cam-smmu-label = "ope", "ope-cdm"; ope_iova_mem_map: iova-mem-map { /* IO region is approximately 3.4 GB */ iova-mem-region-io { @@ -206,7 +211,7 @@ msm_cam_smmu_cpas_cdm { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_smmu 0x800 0x000>; - cam-smmu-label = "cpas-cdm0"; + cam-smmu-label = "cpas-cdm"; qcom,iommu-faults = "non-fatal"; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; cpas_cdm_iova_mem_map: iova-mem-map { @@ -226,12 +231,11 @@ cam-smmu-label = "cam-secure"; qcom,secure-cb; }; - }; qcom,cam-cpas@5c11000 { cell-index = <0>; - compatible = "qcom,cam-cpas"; + compatible = "qcom,cam-cpas", "simple-bus"; label = "cpas"; arch-compat = "cpas_top"; status = "ok"; @@ -239,13 +243,13 @@ reg = <0x5c11000 0x1000>, <0x5c13000 0x4000>; reg-cam-base = <0x11000 0x13000>; + cam_hw_fuse = ; interrupt-names = "cpas_camnoc"; interrupts = ; camnoc-axi-min-ib-bw = <3000000000>; regulator-names = "camss-vdd"; camss-vdd-supply = <&gcc_camss_top_gdsc>; clock-names = - "gcc_camss_ahb_clk", "gcc_camss_top_ahb_clk", "gcc_camss_top_ahb_clk_src", "gcc_camss_axi_clk", @@ -253,7 +257,6 @@ "gcc_camss_nrt_axi_clk", "gcc_camss_rt_axi_clk"; clocks = - <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, <&gcc GCC_CAMSS_AXI_CLK>, @@ -262,51 +265,37 @@ <&gcc GCC_CAMSS_RT_AXI_CLK>; src-clock-name = "gcc_camss_axi_clk_src"; clock-rates = - <0 0 0 0 0 0 0>, - <0 0 80000000 0 19200000 0 0>, - <0 0 80000000 0 150000000 0 0>, - <0 0 80000000 0 200000000 0 0>, - <0 0 80000000 0 300000000 0 0>, - <0 0 80000000 0 300000000 0 0>, - <0 0 80000000 0 300000000 0 0>; - clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", - "svs_l1", "nominal", "turbo"; - qcom,cx-ipeak-gpu-limit = <921600000>; + <0 0 0 0 0 0>, + <0 19200000 0 19200000 0 0>, + <0 80000000 0 150000000 0 0>, + <0 80000000 0 200000000 0 0>, + <0 80000000 0 300000000 0 0>, + <0 80000000 0 300000000 0 0>, + <0 80000000 0 300000000 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; - qcom,msm-bus,name = "cam_ahb"; - qcom,msm-bus,num-cases = <7>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - , - , - , - , - ; - vdd-corners = ; + interconnect-names = "cam_ahb"; + interconnects =<&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_CAMERA_CFG>; + cam-ahb-num-cases = <7>; + cam-ahb-bw-KBps = + <0 0>, <0 133333>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "lowsvs", "lowsvs", "svs", "svs_l1", "svs_l1", "svs_l1", "nominal", "nominal", "nominal", @@ -326,19 +315,12 @@ node-name = "level2-rt0-rd-wr-sum"; traffic-merge-type = ; - qcom,axi-port-name = "cam_hf_0"; ib-bw-voting-needed; qcom,axi-port-mnoc { - qcom,msm-bus,name = - "cam_hf_0_mnoc"; - qcom,msm-bus-vector-dyn-vote; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; + interconnect-names = "cam_hf_0"; + interconnects = + <&mmrt_virt MASTER_CAMNOC_HF + &bimc SLAVE_EBI_CH0>; }; }; @@ -347,18 +329,11 @@ node-name = "level2-nrt0-rd-wr-sum"; traffic-merge-type = ; - qcom,axi-port-name = "cam_sf_0"; qcom,axi-port-mnoc { - qcom,msm-bus,name = - "cam_sf_0_mnoc"; - qcom,msm-bus-vector-dyn-vote; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; + interconnect-names = "cam_sf_0"; + interconnects = + <&mmnrt_virt MASTER_CAMNOC_SF + &bimc SLAVE_EBI_CH0>; }; }; }; @@ -503,7 +478,7 @@ cam_ope_cdm: qcom,ope-cdm0@5c42000 { cell-index = <0>; - compatible = "qcom,cam-ope-cdm2_0"; + compatible = "qcom,cam-ope-cdm2_1"; label = "ope-cdm"; reg = <0x5c42000 0x400>; reg-names = "ope-cdm0"; @@ -665,7 +640,7 @@ cam_tfe_tpg0: qcom,tpg0@5c66000 { cell-index = <0>; - compatible = "qcom,tpgv1"; + compatible = "qcom,tpg101"; reg-names = "tpg0", "top"; reg = <0x5c66000 0x400>, <0x5c11000 0x1000>; @@ -690,10 +665,10 @@ status = "ok"; }; - cam_tfe_tpg1: qcom,tpg0@5c68000 { + cam_tfe_tpg1: qcom,tpg1@5c68000 { cell-index = <1>; - compatible = "qcom,tpgv1"; - reg-names = "tpg0", "top"; + compatible = "qcom,tpg101"; + reg-names = "tpg1", "top"; reg = <0x5c68000 0x400>, <0x5c11000 0x1000>; reg-cam-base = <0x68000 0x11000>; diff --git a/sm6150-camera.dtsi b/sm6150-camera.dtsi new file mode 100644 index 000000000000..1866e20060a2 --- /dev/null +++ b/sm6150-camera.dtsi @@ -0,0 +1,1471 @@ +#include +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy@ac65000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0x0ac65000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x65000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&titan_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm6150l_l3>; + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "svs_l1", "turbo"; + clock-rates = + <0 0 0 0 269333333 0 269333333 0>, + <0 0 0 0 384000000 0 269333333 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy@ac66000{ + cell-index = <1>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0xac66000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x66000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&titan_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm6150l_l3>; + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "svs_l1", "turbo"; + clock-rates = + <0 0 0 0 269333333 0 269333333 0>, + <0 0 0 0 384000000 0 269333333 0>; + + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy@ac67000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0xac67000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x67000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&titan_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm6150l_l3>; + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "svs_l1", "turbo"; + clock-rates = + <0 0 0 0 269333333 0 269333333 0>, + <0 0 0 0 384000000 0 269333333 0>; + status = "ok"; + }; + + cam_cci: qcom,cci@ac4a000 { + cell-index = <0>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4a000 0x4000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_CLK>, + <&camcc CAM_CC_CCI_CLK_SRC>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cci_clk", + "cci_clk_src"; + src-clock-name = "cci_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 0 0 0 0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 33 0>, + <&tlmm 34 0>, + <&tlmm 35 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0x0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0x0>; + label = "ife"; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0cc0 0x0>, + <&apps_smmu 0x0d40 0x0>; + label = "lrme"; + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xd80 0x20>, + <&apps_smmu 0xda0 0x20>; + label = "jpeg"; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0de2 0x0>, + <&apps_smmu 0x0c80 0x0>, + <&apps_smmu 0x0ca0 0x0>, + <&apps_smmu 0x0d00 0x0>, + <&apps_smmu 0x0d20 0x0>; + label = "icp"; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + iova-granularity = <0x15>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10A00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.3 GB */ + iova-region-name = "io"; + iova-region-start = <0x10C00000>; + iova-region-len = <0xCF300000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* qdss region is approximately 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10B00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0c00 0x0>, + <&apps_smmu 0x0c01 0x0>; + label = "cpas-cdm0"; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cpas@ac40000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0xac40000 0x1000>, + <0xac42000 0x5000>; + reg-cam-base = <0x40000 0x42000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + qcom,cpas-hw-ver = <0x150100>; /* Titan v150 v1.0.0 */ + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "gcc_ahb_clk", + "gcc_axi_clk", + "soc_ahb_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "camnoc_axi_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "slow_ahb_clk_src"; + clock-rates = <0 0 0 0 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>; + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; + interconnect-names = "cam_ahb"; + cam-ahb-num-cases = <7>; + interconnects =<&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>; + cam-ahb-bw-KBps = + <0 0>, <0 76500>, <0 76500>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", + "minsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "cci0", + "csid0", "csid1", "csid2", + "ife0", "ife1", "ife2", "ipe0", + "ipe1", "cam-cdm-intf0", "cpas-cdm0", "bps0", + "icp0", "jpeg-dma0", "jpeg-enc0", "lrmecpas0"; + client-axi-port-names = + "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", + "cam_hf_1", "cam_hf_2", "cam_hf_2", + "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", + "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", + "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1"; + client-bus-camnoc-based; + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF0 + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_wr: level2-rt0-wr { + cell-index = <2>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <3>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <4>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <5>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <6>; + node-name = "level1-rt0-wr0"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <7>; + node-name = "level1-rt0-wr1"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_rd0: level1-rt0-rd0 { + cell-index = <8>; + node-name = "level1-rt0-rd0"; + parent-node = <&level2_rt0_rd>; + traffic-merge-type = + ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <9>; + node-name = "level1-rt0-wr2"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr3: level1-rt0-wr3 { + cell-index = <10>; + node-name = "level1-rt0-wr3"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <11>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <12>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr1: level1-nrt0-wr1 { + cell-index = <13>; + node-name = "level1-nrt0-wr1"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <14>; + node-name = "level1-nrt0-rd2"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife2_ubwc_stats_wr: ife2-ubwc-stats-wr { + cell-index = <15>; + node-name = "ife2-ubwc-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_rt0_wr>; + }; + + ife0_ubwc_stats_wr: ife0-ubwc-stats-wr { + cell-index = <16>; + node-name = "ife0-ubwc-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife1_ubwc_stats_wr: ife1-ubwc-stats-wr { + cell-index = <17>; + node-name = "ife1-ubwc-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife0_linear_pdaf_wr: ife0-linear-pdaf-wr { + cell-index = <18>; + node-name = "ife0-linear-pdaf-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife1_linear_pdaf_wr: ife1-linear-pdaf-wr { + cell-index = <19>; + node-name = "ife1-linear-pdaf-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife2_linear_pdaf_wr: ife2-linear-pdaf-wr { + cell-index = <20>; + node-name = "ife2-linear-pdaf-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_rdi_all_rd: ife0-rdi-all-rd { + cell-index = <21>; + node-name = "ife0-rdi-all-rd"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife1_rdi_all_rd: ife1-rdi-all-rd { + cell-index = <22>; + node-name = "ife1-rdi-all-rd"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife2_rdi_all_rd: ife2-rdi-all-rd { + cell-index = <23>; + node-name = "ife2-rdi-all-rd"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom0_rd: custom0-rd { + cell-index = <24>; + node-name = "custom0-rd"; + client-name = "custom0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom1_rd: custom1-rd { + cell-index = <25>; + node-name = "custom1-rd"; + client-name = "custom1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <26>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife4_rdi_all_wr: ife4-rdi-all-wr { + cell-index = <27>; + node-name = "ife4-rdi-all-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + custom1_wr: custom1-wr { + cell-index = <28>; + node-name = "custom1-wr"; + client-name = "custom1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <29>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr3>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <30>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr3>; + }; + + custom0_wr: custom0-wr { + cell-index = <31>; + node-name = "custom0-wr"; + client-name = "custom0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr3>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <32>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <33>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <34>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <35>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <36>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <37>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr1>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <38>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr1>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <39>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <40>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <41>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc", + "lrmecdm"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac48000 { + cell-index = <0>; + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm"; + reg = <0xac48000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "gcc_camera_ahb", + "gcc_camera_axi", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = <0 0 0 0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb3000 { + cell-index = <0>; + compatible = "qcom,csid170"; + reg-names = "csid"; + reg = <0xacb3000 0x1000>; + reg-cam-base = <0xb3000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_csid_clk", + "ife_csid_clk_src", + "ife_cphy_rx_clk", + "cphy_rx_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk", + "ife_axi_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 320000000 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 540000000 0 0 0 600000000 0 0>; + clock-cntl-level = "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe0: qcom,vfe0@acaf000 { + cell-index = <0>; + compatible = "qcom,vfe170"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacaf000 0x4000>, + <0xac42000 0x5000>; + reg-cam-base = <0xaf000 0x42000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk", + "ife_axi_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 360000000 0 0>, + <0 0 0 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 540000000 0 0>, + <0 0 0 0 0 0 600000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_clk_src"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <600000000>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acba000 { + cell-index = <1>; + compatible = "qcom,csid170"; + reg-names = "csid"; + reg = <0xacba000 0x1000>; + reg-cam-base = <0xba000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_csid_clk", + "ife_csid_clk_src", + "ife_cphy_rx_clk", + "cphy_rx_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk", + "ife_axi_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 320000000 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 540000000 0 0 0 600000000 0 0>; + clock-cntl-level = "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe1: qcom,vfe1@acb6000 { + cell-index = <1>; + compatible = "qcom,vfe170"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacb6000 0x4000>, + <0xac42000 0x5000>; + reg-cam-base = <0xb6000 0x42000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk", + "ife_axi_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 360000000 0 0>, + <0 0 0 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 540000000 0 0>, + <0 0 0 0 0 0 600000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_clk_src"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <600000000>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; + status = "ok"; + }; + + cam_csid_lite: qcom,csid-lite@acc8000 { + cell-index = <2>; + compatible = "qcom,csid-lite170"; + reg-names = "csid-lite"; + reg = <0xacc8000 0x1000>; + reg-cam-base = <0xc8000>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_csid_clk", + "ife_csid_clk_src", + "ife_cphy_rx_clk", + "cphy_rx_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 320000000 0 0 0 432000000 0>, + <0 0 0 0 0 0 540000000 0 0 0 600000000 0>; + clock-cntl-level = "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe_lite: qcom,vfe-lite@acc4000 { + cell-index = <2>; + compatible = "qcom,vfe-lite170"; + reg-names = "ife-lite"; + reg = <0xacc4000 0x4000>; + reg-cam-base = <0xc4000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 360000000 0>, + <0 0 0 0 0 0 432000000 0>, + <0 0 0 0 0 0 540000000 0>, + <0 0 0 0 0 0 600000000 0>; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,a5", + "qcom,ipe0", + "qcom,bps"; + num-a5 = <1>; + num-ipe = <1>; + num-bps = <1>; + icp_pc_en; + status = "ok"; + }; + + cam_a5: qcom,a5@ac00000 { + cell-index = <0>; + compatible = "qcom,cam-a5"; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "a5_qgic", "a5_sierra", "a5_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "a5"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "gcc_cam_ahb_clk", + "gcc_cam_axi_clk", + "soc_fast_ahb", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "icp_clk", + "icp_clk_src"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>; + + clock-rates = + <0 0 200000000 0 0 0 0 360000000>, + <0 0 200000000 0 0 0 0 600000000>; + clock-cntl-level = "svs", "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-cfg = <0x73 0x1CF>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac87000 0x3000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&ipe_0_gdsc>; + clock-names = "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk", + "ipe_0_clk_src"; + src-clock-name = "ipe_0_clk_src"; + clocks = <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_IPE_0_CLK>, + <&camcc CAM_CC_IPE_0_CLK_SRC>; + + clock-rates = + <0 0 0 0 360000000>, + <0 0 0 0 432000000>, + <0 0 0 0 480000000>, + <0 0 0 0 540000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac6f000 0x3000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&bps_gdsc>; + clock-names = "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk", + "bps_clk_src"; + src-clock-name = "bps_clk_src"; + clocks = <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>; + + clock-rates = + <0 0 0 0 360000000>, + <0 0 0 0 432000000>, + <0 0 0 0 480000000>, + <0 0 0 0 540000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc@ac4e000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac4e000 0x4000>; + reg-cam-base = <0x4e000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = <0 0 0 0 0 600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "turbo"; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@ac52000{ + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac52000 0x4000>; + reg-cam-base = <0x52000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = <0 0 0 0 0 600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "turbo"; + status = "ok"; + }; + + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; + status = "ok"; + }; + + cam_lrme: qcom,lrme@ac6b000 { + cell-index = <0>; + compatible = "qcom,lrme"; + reg-names = "lrme"; + reg = <0xac6b000 0xa00>; + reg-cam-base = <0x6b000>; + interrupt-names = "lrme"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "lrme_clk_src", + "lrme_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_LRME_CLK_SRC>, + <&camcc CAM_CC_LRME_CLK>; + clock-rates = <0 0 0 0 0 200000000 200000000>, + <0 0 0 0 0 216000000 216000000>, + <0 0 0 0 0 300000000 300000000>, + <0 0 0 0 0 404000000 404000000>, + <0 0 0 0 0 404000000 404000000>, + <0 0 0 0 0 404000000 404000000>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "nominal_l1", "turbo"; + src-clock-name = "lrme_clk_src"; + status = "ok"; + }; +};