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ARM: EXYNOS: Move pm_domains driver to drivers/soc/samsung
Exynos PM domains driver does not have mach-specific dependencies so it can be safely moved out of arm/mach-exynos to drivers/soc. This in future will allow re-using it on ARM64 boards. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]>
This commit is contained in:
Krzysztof Kozlowski
parent
1a695a905c
commit
e465007a7a
3 changed files with 1 additions and 1 deletions
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@ -1,2 +1,3 @@
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obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o exynos3250-pmu.o exynos4-pmu.o \
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exynos5250-pmu.o exynos5420-pmu.o
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obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
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223
drivers/soc/samsung/pm_domains.c
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223
drivers/soc/samsung/pm_domains.c
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@ -0,0 +1,223 @@
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/*
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* Exynos Generic power domain support.
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Implementation of Exynos specific power domain control which is used in
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* conjunction with runtime-pm. Support for both device-tree and non-device-tree
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* based power domain support is included.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/pm_domain.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/sched.h>
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#define INT_LOCAL_PWR_EN 0x7
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#define MAX_CLK_PER_DOMAIN 4
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/*
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* Exynos specific wrapper around the generic power domain
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*/
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struct exynos_pm_domain {
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void __iomem *base;
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char const *name;
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bool is_off;
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struct generic_pm_domain pd;
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struct clk *oscclk;
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struct clk *clk[MAX_CLK_PER_DOMAIN];
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struct clk *pclk[MAX_CLK_PER_DOMAIN];
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struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
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};
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static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
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{
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struct exynos_pm_domain *pd;
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void __iomem *base;
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u32 timeout, pwr;
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char *op;
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int i;
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pd = container_of(domain, struct exynos_pm_domain, pd);
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base = pd->base;
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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if (IS_ERR(pd->asb_clk[i]))
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break;
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clk_prepare_enable(pd->asb_clk[i]);
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}
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/* Set oscclk before powering off a domain*/
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if (!power_on) {
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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if (IS_ERR(pd->clk[i]))
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break;
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pd->pclk[i] = clk_get_parent(pd->clk[i]);
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if (clk_set_parent(pd->clk[i], pd->oscclk))
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pr_err("%s: error setting oscclk as parent to clock %d\n",
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pd->name, i);
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}
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}
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pwr = power_on ? INT_LOCAL_PWR_EN : 0;
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__raw_writel(pwr, base);
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/* Wait max 1ms */
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timeout = 10;
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while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
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if (!timeout) {
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op = (power_on) ? "enable" : "disable";
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pr_err("Power domain %s %s failed\n", domain->name, op);
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return -ETIMEDOUT;
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}
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timeout--;
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cpu_relax();
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usleep_range(80, 100);
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}
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/* Restore clocks after powering on a domain*/
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if (power_on) {
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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if (IS_ERR(pd->clk[i]))
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break;
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if (IS_ERR(pd->pclk[i]))
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continue; /* Skip on first power up */
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if (clk_set_parent(pd->clk[i], pd->pclk[i]))
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pr_err("%s: error setting parent to clock%d\n",
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pd->name, i);
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}
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}
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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if (IS_ERR(pd->asb_clk[i]))
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break;
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clk_disable_unprepare(pd->asb_clk[i]);
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}
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return 0;
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}
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static int exynos_pd_power_on(struct generic_pm_domain *domain)
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{
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return exynos_pd_power(domain, true);
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}
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static int exynos_pd_power_off(struct generic_pm_domain *domain)
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{
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return exynos_pd_power(domain, false);
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}
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static __init int exynos4_pm_init_power_domain(void)
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{
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struct device_node *np;
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for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
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struct exynos_pm_domain *pd;
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int on, i;
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pd = kzalloc(sizeof(*pd), GFP_KERNEL);
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if (!pd) {
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pr_err("%s: failed to allocate memory for domain\n",
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__func__);
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of_node_put(np);
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return -ENOMEM;
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}
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pd->pd.name = kstrdup_const(strrchr(np->full_name, '/') + 1,
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GFP_KERNEL);
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if (!pd->pd.name) {
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kfree(pd);
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of_node_put(np);
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return -ENOMEM;
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}
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pd->name = pd->pd.name;
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pd->base = of_iomap(np, 0);
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if (!pd->base) {
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pr_warn("%s: failed to map memory\n", __func__);
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kfree_const(pd->pd.name);
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kfree(pd);
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continue;
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}
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pd->pd.power_off = exynos_pd_power_off;
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pd->pd.power_on = exynos_pd_power_on;
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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char clk_name[8];
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snprintf(clk_name, sizeof(clk_name), "asb%d", i);
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pd->asb_clk[i] = of_clk_get_by_name(np, clk_name);
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if (IS_ERR(pd->asb_clk[i]))
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break;
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}
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pd->oscclk = of_clk_get_by_name(np, "oscclk");
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if (IS_ERR(pd->oscclk))
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goto no_clk;
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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char clk_name[8];
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snprintf(clk_name, sizeof(clk_name), "clk%d", i);
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pd->clk[i] = of_clk_get_by_name(np, clk_name);
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if (IS_ERR(pd->clk[i]))
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break;
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/*
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* Skip setting parent on first power up.
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* The parent at this time may not be useful at all.
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*/
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pd->pclk[i] = ERR_PTR(-EINVAL);
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}
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if (IS_ERR(pd->clk[0]))
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clk_put(pd->oscclk);
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no_clk:
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on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
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pm_genpd_init(&pd->pd, NULL, !on);
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of_genpd_add_provider_simple(np, &pd->pd);
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}
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/* Assign the child power domains to their parents */
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for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
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struct generic_pm_domain *child_domain, *parent_domain;
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struct of_phandle_args args;
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args.np = np;
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args.args_count = 0;
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child_domain = of_genpd_get_from_provider(&args);
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if (IS_ERR(child_domain))
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continue;
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if (of_parse_phandle_with_args(np, "power-domains",
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"#power-domain-cells", 0, &args) != 0)
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continue;
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parent_domain = of_genpd_get_from_provider(&args);
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if (IS_ERR(parent_domain))
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continue;
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if (pm_genpd_add_subdomain(parent_domain, child_domain))
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pr_warn("%s failed to add subdomain: %s\n",
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parent_domain->name, child_domain->name);
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else
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pr_info("%s has as child subdomain: %s.\n",
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parent_domain->name, child_domain->name);
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}
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return 0;
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}
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core_initcall(exynos4_pm_init_power_domain);
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