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fpga: dfl: afu: add header sub feature support

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The port header register set is always present for port, it is mainly
for capability, control and status of the ports that AFU connected to.

This patch implements header sub feature support. Below user interfaces
are created by this patch.

Sysfs interface:
* /sys/class/fpga_region/<regionX>/<dfl-port.x>/id
  Read-only. Port ID.

Ioctl interface:
* DFL_FPGA_PORT_RESET
  Reset the FPGA Port and its AFU.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Xiao Guangrong <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
This commit is contained in:
Wu Hao 2018-06-30 08:53:32 +08:00 • committed by Greg Kroah-Hartman
commit e4664c0ee4
3 changed files with 102 additions and 1 deletions
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7
Documentation/ABI/testing/sysfs-platform-dfl-port Normal file
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What: /sys/bus/platform/devices/dfl-port.0/id
Date: June 2018
KernelVersion: 4.19
Contact: Wu Hao <[email protected]>
Description: Read-only. It returns id of this port. One DFL FPGA device
may have more than one port. Userspace could use this id to
distinguish different ports under same FPGA device.