From e4782dcbf32016279d5ef87d5c13e417bf2e4e32 Mon Sep 17 00:00:00 2001
From: Hemant Kumar <hemantk@quicinc.com>
Date: Mon, 3 Aug 2020 19:35:38 -0700
Subject: [PATCH] ARM: dts: msm: Change data size for PCIe write halt

Update value from 1MB to 256B for PCI RC 1 (3x2).
This is a software workaround to prevent system
bus deadlock issue with concurrent access of
greater than 256B granularity from two PCIe
ports to DDR.

Change-Id: I9461e97a70f58b7ca3070881f208615a0624f5b6
---
 qcom/lahaina-pcie.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi
index 51c7a9fc778e..ba945b01962d 100644
--- a/qcom/lahaina-pcie.dtsi
+++ b/qcom/lahaina-pcie.dtsi
@@ -330,6 +330,7 @@
 		qcom,boot-option = <0x1>;
 		qcom,drv-supported;
 		qcom,use-19p2mhz-aux-clk;
+		qcom,wr-halt-size = <0x8>;
 		qcom,no-l0s-supported;
 		qcom,slv-addr-space-size = <0x20000000>;
 		qcom,ep-latency = <10>;